[PATCH 0/4] PCI: dwc: Do not enumerate bus before endpoint devices are ready

Niklas Cassel
2025-06-11T14:53:04Z

Hello all,

The DWC PCIe controller driver currently does not follow the PCIe
specification with regards to the delays after link training, before
sending out configuration requests. This series fixes this.

At the same time, PATCH 1/4 addresses a regression where a Plextor
NVMe drive fails to be configured correctly. With this series, the
Plextor NVMe drive works once again.

Kind regards,
Niklas

Niklas Cassel (4):
PCI: dw-rockchip: Do not enumerate bus before endpoint devices are
ready
PCI: qcom: Do not enumerate bus before endpoint devices are ready
PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link
up
PCI: dwc: Reduce LINK_WAIT_SLEEP_MS

drivers/pci/controller/dwc/pcie-designware.c | 13 ++++++++++++-
drivers/pci/controller/dwc/pcie-designware.h | 11 ++++++++---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 7 +++++++
drivers/pci/controller/dwc/pcie-qcom.c | 7 +++++++
4 files changed, 34 insertions(+), 4 deletions(-)

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2.49.0