[PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready

Niklas Cassel
2025-06-13T12:51:32Z

Hello all,

The DWC PCIe controller driver currently does not follow the PCIe
specification with regards to the delays after link training, before
sending out configuration requests. This series fixes this.

At the same time, PATCH 1/4 addresses a regression where a Plextor
NVMe drive fails to be configured correctly. With this series, the
Plextor NVMe drive works once again.

Kind regards,
Niklas

Changes since v2:
-Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS.

Niklas Cassel (6):
PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to
PCIE_RESET_CONFIG_WAIT_MS
PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS
PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
PCI: qcom: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link
up
PCI: dwc: Reduce LINK_WAIT_SLEEP_MS

drivers/pci/controller/dwc/pcie-designware.c | 13 ++++++++++++-
drivers/pci/controller/dwc/pcie-designware.h | 13 +++++++++----
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 +
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
drivers/pci/controller/pcie-rockchip-host.c | 2 +-
drivers/pci/controller/plda/pcie-starfive.c | 2 +-
drivers/pci/pci.h | 9 +--------
7 files changed, 26 insertions(+), 15 deletions(-)