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From: Ed Wildgoose <lists@wildgooses.com>
To: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Ed Wildgoose <lists@wildgooses.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 2/2] rockchip: dts: Enable UART DMA by adding default dma-names property
Date: Wed, 17 Sep 2025 11:49:31 +0000	[thread overview]
Message-ID: <20250917114932.25994-3-lists@wildgooses.com> (raw)
In-Reply-To: <20250917114932.25994-1-lists@wildgooses.com>

Kernel appears to need a dma-names set for DMA to actually enable. Set a
default dma-names property for all UARTs defined in the base rk356x-base
dtsi

This is tested on a Radxa Zero 3W (which has 5x UARTs) and removes the
warnings and enables DMA on this platform

Signed-off-by: Ed Wildgoose <lists@wildgooses.com>
---
 arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
index fd2214b6f..55240f76d 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
@@ -1334,6 +1334,7 @@ uart1: serial@fe650000 {
 		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac0 2>, <&dmac0 3>;
+		dma-names = "tx", "rx";
 		pinctrl-0 = <&uart1m0_xfer>;
 		pinctrl-names = "default";
 		reg-io-width = <4>;
@@ -1348,6 +1349,7 @@ uart2: serial@fe660000 {
 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac0 4>, <&dmac0 5>;
+		dma-names = "tx", "rx";
 		pinctrl-0 = <&uart2m0_xfer>;
 		pinctrl-names = "default";
 		reg-io-width = <4>;
@@ -1362,6 +1364,7 @@ uart3: serial@fe670000 {
 		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac0 6>, <&dmac0 7>;
+		dma-names = "tx", "rx";
 		pinctrl-0 = <&uart3m0_xfer>;
 		pinctrl-names = "default";
 		reg-io-width = <4>;
@@ -1376,6 +1379,7 @@ uart4: serial@fe680000 {
 		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac0 8>, <&dmac0 9>;
+		dma-names = "tx", "rx";
 		pinctrl-0 = <&uart4m0_xfer>;
 		pinctrl-names = "default";
 		reg-io-width = <4>;
@@ -1390,6 +1394,7 @@ uart5: serial@fe690000 {
 		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac0 10>, <&dmac0 11>;
+		dma-names = "tx", "rx";
 		pinctrl-0 = <&uart5m0_xfer>;
 		pinctrl-names = "default";
 		reg-io-width = <4>;
@@ -1404,6 +1409,7 @@ uart6: serial@fe6a0000 {
 		clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac0 12>, <&dmac0 13>;
+		dma-names = "tx", "rx";
 		pinctrl-0 = <&uart6m0_xfer>;
 		pinctrl-names = "default";
 		reg-io-width = <4>;
@@ -1418,6 +1424,7 @@ uart7: serial@fe6b0000 {
 		clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac0 14>, <&dmac0 15>;
+		dma-names = "tx", "rx";
 		pinctrl-0 = <&uart7m0_xfer>;
 		pinctrl-names = "default";
 		reg-io-width = <4>;
@@ -1432,6 +1439,7 @@ uart8: serial@fe6c0000 {
 		clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac0 16>, <&dmac0 17>;
+		dma-names = "tx", "rx";
 		pinctrl-0 = <&uart8m0_xfer>;
 		pinctrl-names = "default";
 		reg-io-width = <4>;
@@ -1446,6 +1454,7 @@ uart9: serial@fe6d0000 {
 		clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac0 18>, <&dmac0 19>;
+		dma-names = "tx", "rx";
 		pinctrl-0 = <&uart9m0_xfer>;
 		pinctrl-names = "default";
 		reg-io-width = <4>;
-- 
2.49.0


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  parent reply	other threads:[~2025-09-17 11:51 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-17 11:49 [PATCH 0/2] arm64: dts: rockchip: fix dma and pinctrl defs Ed Wildgoose
2025-09-17 11:49 ` [PATCH 1/2] arm64: dts: rockchip: correct uart mux for Radxa ZERO 3 Ed Wildgoose
2025-09-18  4:53   ` FUKAUMI Naoki
2025-09-18 15:23     ` Ed W
2025-09-18 16:18       ` [PATCH 1/2] arm64: dts: rockchip: correct uart mux for Radxa ZERO3 Heiko Stübner
2025-09-18 23:57         ` FUKAUMI Naoki
2025-09-19  9:28           ` Ed W
2025-09-19 10:17           ` Heiko Stübner
2025-09-19 10:21             ` FUKAUMI Naoki
2025-09-19  0:13       ` [PATCH 1/2] arm64: dts: rockchip: correct uart mux for Radxa ZERO 3 FUKAUMI Naoki
2025-09-20  8:14   ` Jonas Karlman
2025-09-17 11:49 ` Ed Wildgoose [this message]
2025-09-17 12:22   ` [PATCH 2/2] rockchip: dts: Enable UART DMA by adding default dma-names property Dragan Simic
2025-09-17 14:25     ` Heiko Stübner
2025-09-18  9:32 ` [PATCH 0/2] arm64: dts: rockchip: fix dma and pinctrl defs v2 Ed Wildgoose
2025-09-18  9:32   ` [PATCH 1/2] arm64: dts: rockchip: correct uart mux for Radxa ZERO 3 Ed Wildgoose
2025-09-18  9:32   ` [PATCH 2/2] rockchip: dts: Enable UART DMA by adding default dma-names property Ed Wildgoose
2025-09-18 16:22     ` Heiko Stübner
2025-09-18 16:20   ` [PATCH 0/2] arm64: dts: rockchip: fix dma and pinctrl defs v2 Heiko Stübner

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