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From: Bjorn Helgaas <helgaas@kernel.org>
To: Niklas Cassel <cassel@kernel.org>
Cc: "Frank Li" <Frank.li@nxp.com>,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Kever Yang" <kever.yang@rock-chips.com>,
	"Simon Xue" <xxm@rock-chips.com>,
	"Damien Le Moal" <dlemoal@kernel.org>,
	"Dragan Simic" <dsimic@manjaro.org>,
	"FUKAUMI Naoki" <naoki@radxa.com>,
	"Diederik de Haas" <diederik@cknow-tech.com>,
	"Richard Zhu" <hongxing.zhu@nxp.com>,
	"Lucas Stach" <l.stach@pengutronix.de>,
	"Shawn Guo" <shawnguo@kernel.org>,
	"Sascha Hauer" <s.hauer@pengutronix.de>,
	"Fabio Estevam" <festevam@gmail.com>,
	"Conor Dooley" <conor@kernel.org>,
	"Krzysztof Kozlowski" <krzk@kernel.org>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"Jonathan Hunter" <jonathanh@nvidia.com>,
	"Hans Zhang" <hans.zhang@cixtech.com>,
	linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, kernel@pengutronix.de,
	"Bjorn Helgaas" <bhelgaas@google.com>
Subject: Re: [PATCH v2 1/4] PCI: dwc: Advertise L1 PM Substates only if driver requests it
Date: Mon, 24 Nov 2025 15:22:27 -0600	[thread overview]
Message-ID: <20251124212227.GA2713330@bhelgaas> (raw)
In-Reply-To: <aR2lOZDBEdGVd9On@ryzen>

On Wed, Nov 19, 2025 at 12:08:41PM +0100, Niklas Cassel wrote:
> On Tue, Nov 18, 2025 at 05:34:18PM -0500, Frank Li wrote:
> > On Tue, Nov 18, 2025 at 03:42:15PM -0600, Bjorn Helgaas wrote:
> > > From: Bjorn Helgaas <bhelgaas@google.com>
> > >
> > > L1 PM Substates require the CLKREQ# signal and may also require
> > > device-specific support.  If CLKREQ# is not supported or driver support is
> > > lacking, enabling L1.1 or L1.2 may cause errors when accessing devices,
> > > e.g.,
> > >
> > >   nvme nvme0: controller is down; will reset: CSTS=0xffffffff, PCI_STATUS=0x10
> > >
> > > If the kernel is built with CONFIG_PCIEASPM_POWER_SUPERSAVE=y or users
> > > enable L1.x via sysfs, users may trip over these errors even if L1
> > > Substates haven't been enabled by firmware or the driver.
> > >
> > > To prevent such errors, disable advertising the L1 PM Substates unless the
> > > driver sets "dw_pcie.l1ss_support" to indicate that it knows CLKREQ# is
> > > present and any device-specific configuration has been done.
> > >
> > > Set "dw_pcie.l1ss_support" in tegra194 (if DT includes the
> > > "supports-clkreq' property) and qcom (for cfg_2_7_0, cfg_1_9_0, cfg_1_34_0,
> > > and cfg_sc8280xp controllers) so they can continue to use L1 Substates.
> > >
> > > Based on Niklas's patch:
> > > https://patch.msgid.link/20251017163252.598812-2-cassel@kernel.org
> > >
> > > Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> > > ---
> > >  .../pci/controller/dwc/pcie-designware-ep.c   |  2 ++
> > >  .../pci/controller/dwc/pcie-designware-host.c |  2 ++
> > >  drivers/pci/controller/dwc/pcie-designware.c  | 24 +++++++++++++++++++
> > >  drivers/pci/controller/dwc/pcie-designware.h  |  2 ++
> > >  drivers/pci/controller/dwc/pcie-qcom.c        |  2 ++
> > >  drivers/pci/controller/dwc/pcie-tegra194.c    |  3 +++
> > >  6 files changed, 35 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > index 7f2112c2fb21..ad6c0fd67a65 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > @@ -966,6 +966,8 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)
> > >  	if (ep->ops->init)
> > >  		ep->ops->init(ep);
> > >
> > > +	dw_pcie_hide_unsupported_l1ss(pci);
> > > +
> > 
> > And, I don't think EP need clean L1SS CAP flags. If EP don't support L1SS,
> > it should be force pull down #clkreq.
> 
> I think the problem is that we cannot force pull down CLKREQ# in a generic
> DWC function. That would have to be done in glue driver specific callbacks.
> 
> Bjorn, perhaps we should simply drop the dw_pcie_hide_unsupported_l1ss()
> call from dw_pcie_ep_init_registers(), and consider hiding L1ss for EPs to
> be out of scope for this series.
> 
> That way, we could still queue this series up for 6.19.
> 
> Thoughts from everyone?

Good idea, done locally, thanks!

Bjorn

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  parent reply	other threads:[~2025-11-24 21:22 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-18 21:42 [PATCH v2 0/4] PCI: dwc: Advertise L1 PM Substates only if driver requests it Bjorn Helgaas
2025-11-18 21:42 ` [PATCH v2 1/4] " Bjorn Helgaas
2025-11-18 22:20   ` Frank Li
2025-11-18 22:45     ` Niklas Cassel
2025-11-19  0:45       ` Frank Li
2025-11-18 22:34   ` Frank Li
2025-11-19 11:08     ` Niklas Cassel
2025-11-19 15:58       ` Frank Li
2025-11-20  0:53         ` Shawn Lin
2025-11-24 21:22       ` Bjorn Helgaas [this message]
2025-11-20  7:52     ` Manivannan Sadhasivam
2025-11-20  7:40   ` Manivannan Sadhasivam
2025-11-24 21:19     ` Bjorn Helgaas
2025-11-25  5:25       ` Manivannan Sadhasivam
2025-11-18 21:42 ` [PATCH v2 2/4] PCI: tegra194: Remove unnecessary L1SS disable code Bjorn Helgaas
2025-11-18 21:42 ` [PATCH v2 3/4] PCI: dw-rockchip: Configure L1SS support Bjorn Helgaas
2025-11-18 21:42 ` [PATCH v2 4/4] arm64: dts: rockchip: Add PCIe clkreq stuff for RK3588 EVB1 Bjorn Helgaas
2025-11-24 22:50 ` [PATCH v2 0/4] PCI: dwc: Advertise L1 PM Substates only if driver requests it Bjorn Helgaas

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