Re: [PATCH v2 4/4] arm64: dts: rockchip: Make Jaguar PCIe-refclk pin use pull-up config

Quentin Schulz
2026-02-10T09:50:51Z

Hi Heiko,

On 2/10/26 9:03 AM, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@cherry.de>
>
> Different to RK3588-Tiger, on RK3588-Jaguar the signal enabling the
> PCIe-refclk generator controls a transistor which in turn controls the
> output-enable input of the PI6C557 and there's no external Pull-Up or
> Pull-Down between the SoC and the transistor gate.
>
> On Tiger the pin is directly connected to the PDn input which has an
> internal pull up.
>
> So match that behaviour on Jaguar by changing the pin config to enable
> the SoC's pull-up config.
>

I think we've a different behavior on Jaguar and Tiger (see polarity of
enable-gpios), so this is a bit misleading. I would simply say this
matches the default PU/PD pinconf of the SoC after reset according to
the TRM. It also means we keep the clock generator in reset until the
device driver drives the enable pin. On Tiger, since we would need a
pull-down to have it disabled by default, but that it's only an internal
pull-down on RK3588-side and a pull-up on the clock generator IC-side, I
don't know if that would work and reliably at that if we were to have
opposite internal pull-up/down resistors on each side of the line, hence
the no PU/PD on RK3588 side.

With the commit log reworked:

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>

Thanks!
Quentin