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Wed, 04 Mar 2026 05:29:36 -0800 (PST) Received: from debian.levillagebyca.com ([213.152.28.84]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4851887fa9csm51283605e9.9.2026.03.04.05.29.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 05:29:36 -0800 (PST) From: MidG971 To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, heiko@sntech.de, jonas@kwiboo.se, midgy971@gmail.com, Claude Subject: [PATCH v2] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock Date: Wed, 4 Mar 2026 14:29:57 +0100 Message-Id: <20260304132957.684616-1-midgy971@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260213151452.535527-1-midgy971@gmail.com> References: <20260213151452.535527-1-midgy971@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260304_052939_389891_348229D1 X-CRM114-Status: UNSURE ( 9.64 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (vcc3v3_pi6c_03), with no clock output representation. The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips. The regulator node is kept as-is since it controls the power supply to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node references this regulator as its vdd-supply and provides a proper 100MHz clock output. The pcie3x2 node is updated to include the reference clock, matching the approach used in rk3588-rock-5-itx.dts. Signed-off-by: Claude Signed-off-by: MidG971 --- Changes since v1 [1]: - Drop phy-supply approach entirely (Jonas, Shawn) - Model PI6C20100 as gated-fixed-clock instead - Wire reference clock to pcie3x2 controller - Follow pattern from rk3588-rock-5-itx.dts [1] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/ .../arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts index 69001e4..24befc9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts @@ -56,7 +56,16 @@ }; }; - /* pi6c pcie clock generator */ + /* PI6C20100 PCIe reference clock buffer (100MHz) */ + pcie30_refclk: pcie-clock-generator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_03>; + }; + + /* PI6C20100 power supply - active-high GPIO0_D4 */ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { compatible = "regulator-fixed"; enable-active-high; @@ -553,6 +562,13 @@ }; &pcie3x2 { + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&pcie30_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; -- 2.39.5 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip