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boundary="===============7875389921560390687==" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org --===============7875389921560390687== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="Ickn2VCpN26N0qJ+" Content-Disposition: inline --Ickn2VCpN26N0qJ+ Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jun 17, 2026 at 06:20:19PM +0200, Gerald Loacker wrote: > Hi Conor, >=20 > Am 17.06.2026 um 17:51 schrieb Conor Dooley: > > On Wed, Jun 17, 2026 at 02:23:14PM +0200, Gerald Loacker wrote: > >> Add support for the optional rockchip,clk-lane-phase device tree prope= rty > >> to allow board-specific tuning of the clock lane sampling phase for > >> improved signal integrity across supported data rates. > >> > >> Signed-off-by: Gerald Loacker > >> --- > >> Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml | 7= +++++++ > >> 1 file changed, 7 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-d= phy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml > >> index 03950b3cad08c..0d824d1511bc0 100644 > >> --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml > >> +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml > >> @@ -56,6 +56,13 @@ properties: > >> description: > >> Some additional phy settings are access through GRF regs. > >> =20 > >> + rockchip,clk-lane-phase: > >> + $ref: /schemas/types.yaml#/definitions/uint32 > >> + minimum: 0 > >> + maximum: 7 > >> + description: > >> + Clock lane sampling phase in 40 ps steps. The hardware default = is 3. > >=20 > > Can this instead become rockchip,clk-lane-phase-ps and be listed in the > > actual unit? > > With the -ps suffix, you can then drop the $ref. > > The default should be listed as "default: 3" (or default: 120) > >=20 > > pw-bot: changes-requested > >=20 >=20 > Thanks for the suggestion. >=20 > The phase setting is a hardware tap index (0=E2=80=937) selecting a delay= line > position. The datasheet mentions =E2=80=9Cabout 40 ps=E2=80=9D per step, = but this is not > a calibrated or guaranteed value and may vary with PVT. >=20 > Because of that, I=E2=80=99d prefer to keep the property as an index and > document the approximate delay in the description: >=20 > Clock lane sampling phase selection (hardware tap index 0=E2=80=937). Eac= h step > corresponds to an approximately 40 ps delay as described in the hardware > specification. >=20 > This matches the hardware model more closely. Happy to adjust if needed. >=20 Sure, I think that's fair. > >> + > >> required: > >> - compatible > >> - reg > >> > >> --=20 > >> 2.34.1 > >> >=20 --Ickn2VCpN26N0qJ+ Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCajMO/gAKCRB4tDGHoIJi 0nNiAQDGqdn+tVrfgHKSxX2jDI4GVxuPM/2N7UWyiTmGN1rXPQEAgQ4uRnmAPDwA ghCPMmy7HHNGhVGn8aephG5ofuMtPgg= =h3/b -----END PGP SIGNATURE----- --Ickn2VCpN26N0qJ+-- --===============7875389921560390687== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip --===============7875389921560390687==--