From: Igor Paunovic <royalnet026@gmail.com>
To: Jiaxing Hu <gahing@gahingwoo.com>
Cc: "Igor Paunovic" <royalnet026@gmail.com>,
"Tomeu Vizoso" <tomeu@tomeuvizoso.net>,
"Heiko Stübner" <heiko@sntech.de>,
"Chaoyi Chen" <chaoyi.chen@rock-chips.com>,
alchark@flipper.net, dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 08/10] accel/rocket: add RK3576 NPU (RKNN) support
Date: Fri, 14 Aug 2026 13:08:21 +0200 [thread overview]
Message-ID: <20260814110825.14893-1-royalnet026@gmail.com> (raw)
In-Reply-To: <20260814082652.3852617-1-gahing@gahingwoo.com>
Hi Jiaxing,
Here is the RK3588 column, all 27 operators, ROCKET_SEED=7, scored the
way perch.py scores: a channel is good when its maxdiff (md below)
against max(cpu, output zero point) is at most 1.
Setup: Orange Pi 5 Plus (RK3588), kernel 7.2.0-rc6, the rocket driver
from this kernel's tree rebuilt with my clocks-by-name and devfreq
patches on top, Mesa at bf70ab68a21, teflon delegate, model
mobilenet_v1_1_224_quant.tflite from the Mesa test suite
(md5 4f348b87dca3315d2b3646cf5a3b31cf), per-operator models generated
with the four byte output patch you described. The "correct hw" column
is your chainmodel.py against the same model file. One difference to
flag up front: against this model file chainmodel prints 36/256 for
operator 8 where your table has 34/256, so our model files are not
byte-identical, and the columns below should be read against each
other rather than against your FINDINGS numbers.
op kind correct hw RK3588
0 conv 32/32 md 1 32/32 md 1
1 depthwise 28/32 md 3 28/32 md 3
2 1x1 22/64 md 6 22/64 md 6
3 depthwise 21/64 md 13 21/64 md 13
4 1x1 18/128 md 14 8/128 md 15
5 depthwise 9/128 md 13 3/128 md 15
6 1x1 4/128 md 23 1/128 md 24
7 depthwise 7/128 md 10 3/128 md 12
8 1x1 36/256 md 7 20/256 md 17
9 depthwise 32/256 md 11 22/256 md 13
10 1x1 29/256 md 9 28/256 md 10
11 depthwise 53/256 md 8 48/256 md 11
12 1x1 166/512 md 11 121/512 md 13
13 depthwise 142/512 md 9 137/512 md 12
14 1x1 82/512 md 7 72/512 md 10
15 depthwise 154/512 md 10 115/512 md 15
16 1x1 82/512 md 7 71/512 md 10
17 depthwise 156/512 md 14 141/512 md 21
18 1x1 92/512 md 7 77/512 md 10
19 depthwise 170/512 md 7 152/512 md 12
20 1x1 102/512 md 8 84/512 md 10
21 depthwise 166/512 md 13 150/512 md 12
22 1x1 174/512 md 6 161/512 md 7
23 depthwise 293/512 md 5 261/512 md 7
24 1x1 671/1024 md 6 636/1024 md 5
25 depthwise 718/1024 md 9 684/1024 md 8
26 1x1 572/1024 md 25 574/1024 md 23
Three things stand out from here.
Operators 0 through 3 score identically to your chain simulation --
same good-channel counts, same maxdiff -- including operator 3, the
stride 2 depthwise with the asymmetric padding you suspect for the
first RK3576 divergence. They are not byte-identical to the simulated
hardware: diffing the raw tensors against the requant_hw chain shows a
few hundred elements per surface already off by 1-4 at operators 0-3.
That looks like the same small extra rounding difference that pushes
the scores below your column from operator 4 on; through operator 3 it
just stays under the maxdiff <= 1 scoring threshold.
There is no md 255 anywhere. From operator 4 on, RK3588 sits somewhat
below the simulation (8 vs 18 at op 4, 1 vs 4 at op 6), but the
maxdiff never exceeds 24 across all 27 operators and the deep layers
track the simulation closely (574 vs 572 at op 26).
A control run with ROCKET_SEED=11 keeps the same character: operator 0
still 32/32, no saturated maxdiff anywhere, worst case md 35 at
operator 6.
So from the RK3588 side your read looks right: the deep-layer
compounding is the reference artifact, and the RK3576 collapse from
operator 4 with maxdiff 255 has no counterpart here.
Igor
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next prev parent reply other threads:[~2026-08-14 11:08 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-12 9:40 [PATCH v7 00/10] accel/rocket: RK3576 NPU (RKNN) enablement Jiaxing Hu
2026-08-12 9:40 ` [PATCH v7 01/10] accel/rocket: take the completion register writes under job_lock Jiaxing Hu
2026-08-12 12:47 ` Igor Paunovic
2026-08-12 9:40 ` [PATCH v7 02/10] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core Jiaxing Hu
2026-08-13 7:04 ` Krzysztof Kozlowski
2026-08-12 9:40 ` [PATCH v7 03/10] dt-bindings: power: rockchip: allow resets in a power domain node Jiaxing Hu
2026-08-13 7:06 ` Krzysztof Kozlowski
2026-08-14 8:21 ` Jiaxing Hu
2026-08-12 9:40 ` [PATCH v7 04/10] dt-bindings: iommu: rockchip: allow the RK3576 NPU MMU clock set Jiaxing Hu
2026-08-12 10:45 ` Diederik de Haas
2026-08-13 9:27 ` Jiaxing Hu
2026-08-12 9:41 ` [PATCH v7 05/10] pmdomain/rockchip: add optional per-domain power-on settle delay Jiaxing Hu
2026-08-12 9:41 ` [PATCH v7 06/10] pmdomain/rockchip: cycle optional power-domain resets on power-on Jiaxing Hu
2026-08-12 9:41 ` [PATCH v7 07/10] accel/rocket: select the per-core clock and reset counts from match data Jiaxing Hu
2026-08-12 9:41 ` [PATCH v7 08/10] accel/rocket: add RK3576 NPU (RKNN) support Jiaxing Hu
2026-08-12 12:48 ` Igor Paunovic
2026-08-13 9:26 ` Jiaxing Hu
2026-08-13 9:56 ` Igor Paunovic
2026-08-14 8:26 ` Jiaxing Hu
2026-08-14 11:08 ` Igor Paunovic [this message]
2026-08-12 9:41 ` [PATCH v7 09/10] arm64: dts: rockchip: rk3576: add NPU (RKNN) nodes Jiaxing Hu
2026-08-12 9:41 ` [PATCH v7 10/10] arm64: dts: rockchip: rk3576-rock-4d: enable NPU Jiaxing Hu
2026-08-12 10:20 ` Chaoyi Chen
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