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[2001:4c4e:1b90:c200:e824:df01:4b0e:c292]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49987b50869sm174877235e9.0.2026.08.18.00.29.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Aug 2026 00:29:53 -0700 (PDT) From: Igor Paunovic To: Nicolas Dufresne , Tomeu Vizoso Cc: Igor Paunovic , Heiko Stuebner , Jiaxing Hu , Oded Gabbay , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org Subject: Re: [RFC] accel/rocket: DVFS on RK3588 - a hardware constraint, and some numbers Date: Tue, 18 Aug 2026 09:27:43 +0200 Message-ID: <20260818072936.41844-1-royalnet026@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: <20260801131656.58450-1-royalnet026@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260818_002956_407997_6653F3DC X-CRM114-Status: GOOD ( 13.94 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Hi Nicolas, > I'm only looking at the RK3588, I suppose all the issues below > related to RK3576 ? No - everything in the RFC is RK3588 (Orange Pi 5 Plus, all three cores). RK3576 is Jiaxing's enablement series and has its own set of problems; nothing I reported came from there. I went through the four commits on rock5b-npu-poc-4 today. We converged on the same shape independently, which is encouraging: 200 MHz kept as the suspend rate, a single devfreq instance modelled on panfrost with busy time aggregated across the three cores, and a cooling device on top. Your ~2.5x on the SSD pipeline also matches the 2.58x I measured here with simple_ondemand against the 200 MHz pin. The TF-A pointer (rk3588_clk.c, PVTPLL vs normal path) is the most valuable part for me - it names the mechanism behind the power-on ack failure I could only demonstrate empirically. I will reference it in the cover letter once I have checked the firmware source myself. Status here: after Tomeu's go-ahead I am preparing the series - bindings, a full-range OPP table in the DT (300-1000 MHz plus the 200 MHz suspend point, so essentially the table you ended up with), a safe-rate-on-suspend guard, the devfreq itself, and a hold-all guard that resumes all cores around any rate change. The guard is ordered before the devfreq patch so no bisect point has scaling without it. The one hard dependency is my "request the core clocks by name" v2, still waiting for pickup. Agreed on OPP staying optional - the plan in my series is that the driver keeps working with no OPP table in the DT, which I saw you intend to fix on your side as well. One path worth checking in your PoC, because it is the one that made me write the hold-all guard: a sysfs min_freq/max_freq write while all three cores are runtime-suspended goes straight to clk_set_rate, which can select the PVTPLL path while the domain is off - exactly the case your TF-A reference explains. With the guard in place I measured that write waking the cores and completing cleanly. One difference in test conditions worth keeping in mind: my numbers are with the vendor bl31 that EDK2 bundles, yours is upstream TF-A. Comparing SCMI behaviour on both seems wise before either of us claims anything firmware-specific. Thank you for the "take whatever you like" - anything I lift will carry credit, and I will Cc you on the series. Regards, Igor _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip