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From: Igor Paunovic <royalnet026@gmail.com>
To: Jiaxing Hu <gahing@gahingwoo.com>,
	Tomeu Vizoso <tomeu@tomeuvizoso.net>,
	Oded Gabbay <ogabbay@kernel.org>
Cc: Igor Paunovic <royalnet026@gmail.com>,
	Heiko Stuebner <heiko@sntech.de>,
	Chaoyi Chen <chaoyi.chen@rock-chips.com>,
	Alexey Charkov <alchark@flipper.net>,
	Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	dri-devel@lists.freedesktop.org,
	linux-rockchip@lists.infradead.org, iommu@lists.linux.dev,
	linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8 02/12] accel/rocket: wait for a running IRQ handler before resetting a core
Date: Wed, 19 Aug 2026 08:51:45 +0200	[thread overview]
Message-ID: <20260819065146.5904-1-royalnet026@gmail.com> (raw)
In-Reply-To: <20260819013609.1613919-1-gahing@gahingwoo.com>

Hi Jiaxing,

Thank you for the round history and for running my archive check - the
zero stall/paging count telling us the MMU is not responding at all is
a better characterization than anything I had. put_noidle vs
put_autosuspend with a separately forced suspend/resume sounds like the
right de-confounding split; I will watch for the result.

Here is the induced reset test I promised, run this morning.

Setup: RK3588 (Orange Pi 5 Plus), all three cores bound. My 7.2-rc6
tree with exactly two rocket changes from your series - 1/12 and 2/12 -
plus one local test-only patch lowering JOB_TIMEOUT_MS to 2 ms so that
healthy jobs (~5 ms at this clock) cross the timeout deterministically.
No other rocket changes; in particular my lifecycle series is not
applied. PROVE_LOCKING=y and DEBUG_ATOMIC_SLEEP=y. Serial console
captured on a second machine for the whole session.

Protocol, built around the trap you described - the RK3576 symptom
emits from rk_iommu_enable() on the next attach, not from the reset
itself: 20 scheduler-driven runs over the model set with all three
cores active, a follow-up inference after every induced reset, then a
forced autosuspend cycle and one more inference. Two full passes, at
console_loglevel 8 and 4, because synchronous serial printing on this
path can perturb the timing.

Results:

- Pass 1 (loglevel 8): 12 induced resets. Pass 2 (loglevel 4): 8.
- Every reset recovered. Zero MMU_DTE_ADDR, zero "Error during raw
  reset", zero lockdep or atomic-sleep hits across both passes.
- Outputs matched the oracle in 48/48 checks per pass, including the
  inference after the forced suspend/resume.
- All three cores returned to runtime-suspended between rounds; the
  domain did drop and come back cleanly after every reset.

So on RK3588 with 1/12+2/12 the block comes back every time, and your
non-recovery does not reproduce. Combined with your archive result
this is consistent with the failure being RK3576-specific on the
platform/IOMMU side rather than rocket-wide.

Two honest limits on what this run shows:

1. All resets ran with three cores bound. Isolating a single core
   requires unbinding the other two, and without my pending lifecycle
   fixes that path is not safe on this tree (the list corruption I
   reported on Aug 12), so I skipped it deliberately rather than test
   through a known-broken path.

2. This run alone says nothing about the race 1/12+2/12 close. The
   same protocol on the base without those two patches is queued as a
   separate build; only that differential earns a Tested-by, and when
   it lands the tag will carry its conditions:
   # RK3588, three cores, induced reset, JOB_TIMEOUT_MS=2

Raw logs (dmesg, per-run outputs, serial capture) are kept; happy to
share any of it on request.

Regards,
Igor

_______________________________________________
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Linux-rockchip@lists.infradead.org
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  reply	other threads:[~2026-08-19  6:52 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-17 11:35 [PATCH v8 00/12] accel/rocket: RK3576 NPU (RKNN) enablement Jiaxing Hu
2026-08-17 11:35 ` [PATCH v8 01/12] accel/rocket: take the completion register writes under job_lock Jiaxing Hu
2026-08-17 11:35 ` [PATCH v8 02/12] accel/rocket: wait for a running IRQ handler before resetting a core Jiaxing Hu
2026-08-17 12:56   ` Igor Paunovic
2026-08-19  1:36     ` Jiaxing Hu
2026-08-19  6:51       ` Igor Paunovic [this message]
2026-08-19  7:24         ` Jiaxing Hu
2026-08-19  7:35           ` Igor Paunovic
2026-08-17 11:35 ` [PATCH v8 03/12] accel/rocket: factor the completion tail out of the IRQ handler Jiaxing Hu
2026-08-17 12:51   ` Igor Paunovic
2026-08-17 11:35 ` [PATCH v8 04/12] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core Jiaxing Hu
2026-08-18 23:09   ` Rob Herring (Arm)
2026-08-17 11:35 ` [PATCH v8 05/12] dt-bindings: power: rockchip: allow resets in a power domain node Jiaxing Hu
2026-08-17 11:35 ` [PATCH v8 06/12] dt-bindings: iommu: rockchip: describe the RK3576 NPU MMU Jiaxing Hu
2026-08-17 11:35 ` [PATCH v8 07/12] pmdomain/rockchip: add optional per-domain power-on settle delay Jiaxing Hu
2026-08-17 11:35 ` [PATCH v8 08/12] pmdomain/rockchip: cycle optional power-domain resets on power-on Jiaxing Hu
2026-08-17 11:36 ` [PATCH v8 09/12] accel/rocket: select the per-core clock and reset counts from match data Jiaxing Hu
2026-08-17 11:36 ` [PATCH v8 10/12] accel/rocket: add RK3576 NPU (RKNN) support Jiaxing Hu
2026-08-18  8:59   ` Uwe Kleine-König
2026-08-17 11:36 ` [PATCH v8 11/12] arm64: dts: rockchip: rk3576: add NPU (RKNN) nodes Jiaxing Hu
2026-08-17 11:36 ` [PATCH v8 12/12] arm64: dts: rockchip: rk3576-rock-4d: enable NPU Jiaxing Hu

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