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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The RK3588 PCIe endpoint controller exposes its MSI-X table at BAR4+0x4000 and its PBA at BAR4+0x5000. Describe both as reserved regions so EPF drivers can select the hardware-owned layout. The regular DesignWare MSI-X interrupt path reads an EPF-owned table through epf_bar[]. A reserved, hardware-owned table has no such backing. Record whether the layout selected for each function matches the hardware-owned layout, and use the controller MSI-X doorbell on RK3588 only in that case. Continue to use the regular path for EPF-owned layouts. Signed-off-by: Koichiro Den --- .../pci/controller/dwc/pcie-designware-ep.c | 21 ++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-dw-rockchip.c | 28 +++++++++++++++++-- 3 files changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 147b043589f0..bc2b63814dea 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -736,6 +736,26 @@ static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) return val + 1; } +static bool +dw_pcie_ep_msix_layout_is_hw_owned(struct dw_pcie_ep *ep, + const struct pci_epc_msix_layout *layout) +{ + const struct pci_epc_features *features; + struct pci_epc_msix_layout hw_layout; + + if (!ep->ops->get_features) + return false; + + features = ep->ops->get_features(ep); + if (pci_epc_get_hw_msix_layout(features, &hw_layout)) + return false; + + return layout->table_bar == hw_layout.table_bar && + layout->table_offset == hw_layout.table_offset && + layout->pba_bar == hw_layout.pba_bar && + layout->pba_offset == hw_layout.pba_offset; +} + static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u16 nr_irqs, const struct pci_epc_msix_layout *layout) @@ -764,6 +784,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, reg = ep_func->msix_cap + PCI_MSIX_PBA; val = layout->pba_offset | layout->pba_bar; dw_pcie_ep_writel_dbi(ep, func_no, reg, val); + ep_func->msix_hw_owned = dw_pcie_ep_msix_layout_is_hw_owned(ep, layout); dw_pcie_dbi_ro_wr_dis(pci); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index de4b245b1758..043c39b5881d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -495,6 +495,7 @@ struct dw_pcie_ep_func { u8 func_no; u8 msi_cap; /* MSI capability offset */ u8 msix_cap; /* MSI-X capability offset */ + bool msix_hw_owned; u8 bar_to_atu[PCI_STD_NUM_BARS]; struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 731d93663cca..d622723dfcf8 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -120,6 +120,7 @@ struct rockchip_pcie { struct rockchip_pcie_of_data { enum dw_pcie_device_mode mode; const struct pci_epc_features *epc_features; + bool msix_doorbell; }; static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg) @@ -481,6 +482,8 @@ static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, unsigned int type, u16 interrupt_num) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); + struct dw_pcie_ep_func *ep_func; switch (type) { case PCI_IRQ_INTX: @@ -488,6 +491,12 @@ static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, case PCI_IRQ_MSI: return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); case PCI_IRQ_MSIX: + ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); + if (rockchip->data->msix_doorbell && ep_func && + ep_func->msix_hw_owned) + return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no, + interrupt_num); + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); default: dev_err(pci->dev, "UNKNOWN IRQ type\n"); @@ -517,12 +526,24 @@ static const struct pci_epc_bar_rsvd_region rk3588_bar4_rsvd[] = { .offset = 0x0, .size = 0x2000, }, + { + /* MSI-X Table (BAR4: MSI-X Table) */ + .type = PCI_EPC_BAR_RSVD_MSIX_TBL_RAM, + .offset = 0x4000, + .size = SZ_4K, + }, + { + /* MSI-X PBA (BAR4: MSI-X PBA) */ + .type = PCI_EPC_BAR_RSVD_MSIX_PBA_RAM, + .offset = 0x5000, + .size = SZ_4K, + }, }; /* - * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of - * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver, - * so mark it as RESERVED. + * BAR4 on RK3588 exposes the DMA and ATU Port Logic Structures and the MSI-X + * table and PBA to the host regardless of iATU settings for BAR4. This means + * that BAR4 cannot be used by an EPF driver, so mark it as RESERVED. */ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = { DWC_EPC_COMMON_FEATURES, @@ -841,6 +862,7 @@ static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3568 = { static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3588 = { .mode = DW_PCIE_EP_TYPE, .epc_features = &rockchip_pcie_epc_features_rk3588, + .msix_doorbell = true, }; static const struct of_device_id rockchip_pcie_of_match[] = { -- 2.51.0 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip