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[2001:4c4e:1b83:1700:c106:e30f:6c82:7c62]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce309e418sm83442895e9.13.2026.09.02.04.04.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 04:04:50 -0700 (PDT) From: Igor Paunovic To: Huseyin BIYIK Cc: Igor Paunovic , Nicolas Dufresne , Tomeu Vizoso , Heiko Stuebner , Jiaxing Hu , Oded Gabbay , Jonas Karlman , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org Subject: Re: [RFC] accel/rocket: DVFS on RK3588 - a hardware constraint, and some numbers Date: Wed, 2 Sep 2026 13:04:27 +0200 Message-ID: <20260902110432.22069-1-royalnet026@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: <20260801131656.58450-1-royalnet026@gmail.com> <286e8418-fae6-4979-96d1-e13abb04b3a1@kwiboo.se> <3204a0d0-969d-4ac6-adfd-29c57f1c3e0a@kwiboo.se> <20260819125932.5853-1-royalnet026@gmail.com> <82c8b17e-7215-45ea-84d1-9991ba6fb541@kwiboo.se> <20260819184807.6665-1-royalnet026@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260902_040453_023164_AFE6FCCE X-CRM114-Status: GOOD ( 14.77 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Hi Huseyin, > No you can even read them from userspace with mmap. i think there > is also a firewall configuration where you can restrict the access > per ip core, but default configuration should not require any EL > escalation. You were right, and here is the number that proves it. On my daily kernel, from plain userspace mmap, the GPU PVTPLL counter reads: GPU_GRF+0x18 (STATUS1) = 0x412 -> 1042 MHz measured, at the stock 1000 MHz PVTPLL operating point so the written rate really is just nominal calibration, and the actual ring runs 4.2% above it on this sample. One detail against your note: on my board the live value shows up in STATUS1 (OSC_CNT_AVG), while STATUS0.OSC_CNT stays zero. Thank you for mmm and for the TF-A pointer - both did exactly what you said. The NPU counter is another story, and I can now bound it tightly. With the ring alive and clocking the NPU at 1 GHz (CON74[0]=1, CON0_L=0x103, length 12, CAL_CNT=24), NPU_GRF+0x24 stays zero from both kernel ioremap and userspace mmap, after eliminating every lever reachable from the non-secure side: - counter input select already xin_osc0_func (CON74[4]=1) - REF_CNT (+0x1c) tried both as found (0) and set to 0x18 - every gate bit in CLKGATE_CON(27/28/29) opened, one register at a time and all together (27/28 were already fully ungated) - CON registers read and write fine throughout - only STATUS0/1 stay zero The GPU counter counts out of the box with its pvtm gates closed, so none of the pvtm clocks are the reference. SkatterBencher's rk3588-tools hit the same wall ("NPU PVTPLL is not working", with the sel flip left unimplemented), so this seems to be a wall and not my setup. That leaves two candidates, and one of them is the firewall you mentioned: either the NPU status words are restricted for non-secure masters (per-ip-core firewall), or the counter is simply not wired on the NPU instance. Have you ever seen a nonzero NPU read on silicon, for example through your d2d6928641ba get_rate path from EL3? My next step is to cherry-pick that commit into my BL31: if EL3 also reads zero, the silicon answer wins. Jonas: the GPU result above also answers the OSC counter offset question from the pclk thread - GPU STATUS1 sits at GRF_GPU+0x18 and counts without any setup. I added a GRF_NPU catalog entry to mmm while testing (start 0xFD5A200C, per the TF-A offsets). Happy to send it as a PR if you want it despite the dead counter. Igor _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip