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[2001:4c4e:1b89:6200:3434:ab95:a407:e573]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed3706sm12709656f8f.18.2026.09.03.02.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2026 02:17:05 -0700 (PDT) From: Igor Paunovic To: Huseyin BIYIK Cc: Igor Paunovic , Nicolas Dufresne , Tomeu Vizoso , Heiko Stuebner , Jiaxing Hu , Oded Gabbay , Jonas Karlman , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org Subject: Re: [RFC] accel/rocket: DVFS on RK3588 - a hardware constraint, and some numbers Date: Thu, 3 Sep 2026 11:16:37 +0200 Message-ID: <20260903091646.7183-1-royalnet026@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260902110432.22069-1-royalnet026@gmail.com> References: <20260801131656.58450-1-royalnet026@gmail.com> <286e8418-fae6-4979-96d1-e13abb04b3a1@kwiboo.se> <3204a0d0-969d-4ac6-adfd-29c57f1c3e0a@kwiboo.se> <20260819125932.5853-1-royalnet026@gmail.com> <82c8b17e-7215-45ea-84d1-9991ba6fb541@kwiboo.se> <20260819184807.6665-1-royalnet026@gmail.com> <20260902110432.22069-1-royalnet026@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260903_021708_471969_28BE180F X-CRM114-Status: GOOD ( 11.83 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Yesterday I wrote: > My next step is to cherry-pick that commit into my BL31: if EL3 > also reads zero, the silicon answer wins. Done this morning, and the answer is in: the firewall wins, and Huseyin called it right. Setup: d2d6928641ba cherry-picked onto the upstream TF-A v2.12 my board runs (banner v2.12.0-10-g70d814213 verified over UART after flashing). With that BL31, clk_get_rate() goes through EL3 reading the PVTPLL status words directly. NPU, from EL3: NPUGRF+0x24 reads a real value. clk_get_rate() returns exactly 1000000000 at the 1 GHz OPP and exactly 700000000 at 700 MHz. At the same moment, the same register read from a kernel module (EL1) still returns 0x00000000. Same register, same instant: secure world sees the counter, non-secure gets zeros. So the counter is alive in silicon, and yesterday's dead end was the per-ip-core access restriction you suspected - not a missing clock and not an unbonded counter. GPU, from EL3, as cross-check under glmark2 load: five consecutive reads gave 1048, 1053, 1047, 1054, 1049 MHz at the 1000 MHz OPP - live jitter, matching the 1042 I measured from userspace mmap yesterday. So EL3 reports raw measurements, which makes the NPU result the more interesting one: The NPU PVTPLL apparently LOCKS to its target (readback == nominal to the MHz, at two operating points), while the GPU one free-runs about 5% above nominal. Same register layout, same CON2 contents as far as I can see - do you know what makes the two instances behave differently? Practical upshot for this series: with your TF-A commit in BL31, plain clk_get_rate() gives the kernel measured rates with no GRF access from the non-secure side at all. That is the clean telemetry path for rocket DVFS, and one more reason your commit earns its keep on RK3588. One honest gap: I could not yet take the voltage-vs-frequency curve (my devfreq module holds the NPU rail at 850 mV as a regulator consumer, so undervolting from a second consumer is refused). Future work. Igor _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip