From: Igor Paunovic <royalnet026@gmail.com>
To: "Hüseyin BIYIK" <boogiepop@gmx.com>
Cc: Igor Paunovic <royalnet026@gmail.com>,
Nicolas Dufresne <nicolas@ndufresne.ca>,
Tomeu Vizoso <tomeu@tomeuvizoso.net>,
Heiko Stuebner <heiko@sntech.de>,
Jiaxing Hu <gahing@gahingwoo.com>,
Oded Gabbay <ogabbay@kernel.org>, Jonas Karlman <jonas@kwiboo.se>,
dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org
Subject: Re: [RFC] accel/rocket: DVFS on RK3588 - a hardware constraint, and some numbers
Date: Thu, 1 Oct 2026 13:49:58 +0200 [thread overview]
Message-ID: <20261001114958.24236-1-royalnet026@gmail.com> (raw)
In-Reply-To: <20260903185147.49411-1-royalnet026@gmail.com>
Hi Hüseyin,
A correction to my two mails of 3 September in this thread, where I
told you that the NPU readback from BL31 was the counter and not the
request. You were right and I was wrong.
The reading stopped at clk_scmi_npu_get_rate() in rk3588_clk.c. The
call goes through plat_scmi_clock_get_rate() in
plat/rockchip/common/scmi/scmi_clock.c, which returns the last
accepted rate (clock->cur_rate) whenever ->get_rate() returns 0. So
"no fallback" was false: a zero in NPUGRF+0x24 comes back as the last
rate the firmware accepted, which at an accepted OPP is the rate asked
for, and that is exactly what I saw, 1000000000 in all 104 samples at
the 1 GHz OPP. The GPU readback on the same BL31 moved (1047 to
1054 MHz), so on the GPU a counter is being read. The TRM lists NPU
GRF 0x24 as NPU_GRF_NPUTOP_CON, but the GPU status word your commit
reads at GPU GRF 0x18 is not in the TRM either, so the offset alone
settles nothing. What I have is the EL1 read of NPU GRF 0x24, 0 in all
20 samples, and this: on 15 September, with the rail pinned at 850 mV,
requests of 800, 900 and 1000 MHz read back exactly 800, 900 and 1000,
although your table programs the same ring length for all three. One
counter cannot return three numbers for one ring at one voltage.
What stands: the CRU selector (CLKSEL_CON74 bit 0) shows the PVTPLL
path, and the inference numbers in those mails and in the v2 cover are
unchanged. What I withdraw: "secure world sees the counter", "the
counter is alive in silicon", "EL3 reports raw measurements" and "the
readback is the counter"; "constant to the MHz", which I offered in
place of "locks", goes with them as a statement about the hardware;
and "the clean telemetry path for rocket DVFS" holds for the GPU and
the CPUs, not for the NPU. The actual NPU PVTPLL frequency is not
measured on my board. I will say the same in the v3 cover. Sorry for
arguing with you about it.
An LLM (Claude) found the fallback and drafted this mail in English;
I read it back in Serbian before sending.
Igor
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next prev parent reply other threads:[~2026-10-01 11:50 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-01 13:16 [RFC] accel/rocket: DVFS on RK3588 - a hardware constraint, and some numbers Igor Paunovic
2026-08-01 19:32 ` Jiaxing Hu
2026-08-02 12:04 ` Igor Paunovic
2026-08-15 18:24 ` Tomeu Vizoso
2026-08-17 18:22 ` Nicolas Dufresne
2026-08-18 7:27 ` Igor Paunovic
2026-08-18 12:12 ` Jonas Karlman
2026-08-18 12:30 ` Jonas Karlman
2026-08-19 5:52 ` Igor Paunovic
2026-08-19 9:40 ` Jonas Karlman
2026-08-19 12:59 ` Igor Paunovic
2026-08-19 16:20 ` Jonas Karlman
2026-08-19 18:48 ` Igor Paunovic
2026-08-19 20:07 ` Hüseyin BIYIK
2026-09-02 11:04 ` Igor Paunovic
2026-09-03 9:16 ` Igor Paunovic
[not found] ` <2f88072c-6aa3-4294-a35d-722d1c7a405c@email.android.com>
2026-09-03 18:51 ` Igor Paunovic
2026-10-01 11:49 ` Igor Paunovic [this message]
2026-09-04 11:08 ` Jiaxing Hu
2026-09-04 12:46 ` Igor Paunovic
2026-09-05 5:13 ` Jiaxing Hu
2026-09-05 7:01 ` Igor Paunovic
2026-08-19 18:47 ` Nicolas Dufresne
2026-09-04 11:19 ` Jiaxing Hu
[not found] <DKDOBW9CJ2Y3.10EEIZDTXPYJZ@cknow-tech.com>
2026-08-01 14:40 ` Igor Paunovic
2026-08-01 16:29 ` Diederik de Haas
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