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Mon, 05 Oct 2026 15:12:59 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a8533aba95sm1719425a91.2.2026.10.05.15.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Oct 2026 15:12:58 -0700 (PDT) From: Coia Prant To: Vinod Koul Cc: Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Coia Prant Subject: [PATCH v10 1/2] dt-bindings: phy: rockchip: naneng-combphy: add rockchip,sgmii-mac-sel property Date: Tue, 6 Oct 2026 06:12:28 +0800 Message-ID: <20261005221229.1095843-2-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261005221229.1095843-1-coiaprant@gmail.com> References: <20261005221229.1095843-1-coiaprant@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261005_151301_076308_7D3038A3 X-CRM114-Status: GOOD ( 12.26 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org On RK3568, the SGMII interface can be routed to either GMAC0 or GMAC1 via the pipe_sgmii_mac_sel bit in the pipe GRF registers. Add the optional "rockchip,sgmii-mac-sel" property to allow the device tree to select which GMAC controller is used for SGMII. The property takes a value of 0 (GMAC0) or 1 (GMAC1). The hardware reset value is 1 (GMAC1), but this can be overridden by setting the property to 0 for boards where SGMII is connected to GMAC0. This is necessary for boards such as the Ariaboard Photonicat, where the SGMII interface is connected to GMAC0 and needs to be explicitly configured. Signed-off-by: Coia Prant --- .../bindings/phy/phy-rockchip-naneng-combphy.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml index 379b08bd9e97a..8e898bce9af73 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -80,6 +80,15 @@ properties: description: Some additional pipe settings are accessed through GRF regs. + rockchip,sgmii-mac-sel: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + default: 1 + description: + Select gmac0 or gmac1 to be used as SGMII controller. + The hardware reset value is GMAC1 (1). Set this to 0 to route + SGMII to GMAC0. + "#phy-cells": const: 1 @@ -105,6 +114,10 @@ allOf: maxItems: 1 reset-names: maxItems: 1 + rockchip,sgmii-mac-sel: true + else: + properties: + rockchip,sgmii-mac-sel: false - if: properties: compatible: -- 2.47.3 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip