* [PATCH] clk: rockchip: rk3288: prefer vdpu for vcodec clock source
@ 2017-05-14 6:50 Randy Li
2017-05-14 15:06 ` Heiko Stuebner
0 siblings, 1 reply; 2+ messages in thread
From: Randy Li @ 2017-05-14 6:50 UTC (permalink / raw)
To: linux-rockchip
Cc: mturquette, sboyd, heiko, linux-clk, linux-arm-kernel,
linux-kernel, myy, Randy Li
The RK3288 CRU system clock solution would suggest use
the vdpu clock source for the VPU(aclk_vpu and hclk_vpu).
Reading the registers of VPU(both VEPU and VDPU) would become all high
when the vepu is used as the clock source. It may be a bug in the SoC,
not sure whether it is fixed at RK3288W.
Signed-off-by: Randy Li <ayaka@soulik.info>
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 68ba7d4..886b249 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -198,7 +198,7 @@ PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
-PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vepu", "aclk_vdpu" };
+PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" };
PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m",
"sclk_otgphy0_480m" };
PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
--
2.9.3
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: rockchip: rk3288: prefer vdpu for vcodec clock source
2017-05-14 6:50 [PATCH] clk: rockchip: rk3288: prefer vdpu for vcodec clock source Randy Li
@ 2017-05-14 15:06 ` Heiko Stuebner
0 siblings, 0 replies; 2+ messages in thread
From: Heiko Stuebner @ 2017-05-14 15:06 UTC (permalink / raw)
To: Randy Li; +Cc: linux-rockchip, mturquette, sboyd, linux-clk, linux-arm-kernel
Hi Randy,
Am Sonntag, 14. Mai 2017, 14:50:09 CEST schrieb Randy Li:
> The RK3288 CRU system clock solution would suggest use
> the vdpu clock source for the VPU(aclk_vpu and hclk_vpu).
>
> Reading the registers of VPU(both VEPU and VDPU) would become all high
> when the vepu is used as the clock source. It may be a bug in the SoC,
> not sure whether it is fixed at RK3288W.
I don't think that is a case of "preference". GRF_SOC_CON0[7] indicates
that value 0 means vepu gets selected as vcodec clock and value 1 means
vdpu gets selected as vcodec.
The array values below are supposed to match these values, so array
index 0 represents the clock for value 0 and so on. So this is really only
a description of the hardware clock layout.
If you want to actually switch the mux value, please assign the vcodec
clock an id and use the assigned-clocks mechanism in the devicetree.
Heiko
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