Re: [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399

Heiko Stuebner
2018-03-23T08:26:00Z

Am Dienstag, 20. März 2018, 03:06:28 CET schrieb Lin Huang:
> Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
> and these two PLL may change their frequency. If we do not
> assign right id to pclk_ddr and hclk_sd, they will alway use
> default cur register value, and may get the frequency
> exceed their signed off frequency. So assign correct Id
> for them, then we can assign frequency for them in dts.
>
> Change-Id: I6c4d15d37ddabe4ed34e2351cf26e660672ae9ee
> Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> Reviewed-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

applied for 4.17 after dropping the Change-Id

Thanks
Heiko