From: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
To: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Cc: huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
Michael Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
elaine.zhang-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [RESEND PATCH v2 1/5] clk: rockchip: add more mux parameters for new pll sources
Date: Wed, 09 Mar 2016 02:12:31 +0100 [thread overview]
Message-ID: <2242962.kh0Ty0L2C4@phil> (raw)
In-Reply-To: <1456827275-8035-2-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Am Dienstag, 1. März 2016, 18:14:31 schrieb Xing Zheng:
> Thers are only two parent PLLs that APLL and GPLL for core on the
> previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
> GPLL as alternate parent when core is switching freq.
>
> Since RK3399 big.LITTLE architecture, we need to select and adapt
> more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.
>
> Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
note to self: looks good to go
next prev parent reply other threads:[~2016-03-09 1:12 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-01 10:14 [RESEND PATCH v2 0/5] Add more clock compatible features and support the RK3399 clock Xing Zheng
2016-03-01 10:14 ` [RESEND PATCH v2 1/5] clk: rockchip: add more mux parameters for new pll sources Xing Zheng
[not found] ` <1456827275-8035-2-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-03-09 1:12 ` Heiko Stuebner [this message]
2016-03-01 10:14 ` [RESEND PATCH v2 2/5] clk: rockchip: Add support for multiple clock providers Xing Zheng
2016-03-01 10:14 ` [RESEND PATCH v2 3/5] clk: rockchip: add new pll-type for rk3399 and similar socs Xing Zheng
2016-03-09 1:22 ` Heiko Stuebner
2016-03-09 2:20 ` Xing Zheng
2016-03-01 10:14 ` [RESEND PATCH v2 4/5] clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type Xing Zheng
2016-03-01 10:15 ` [RESEND PATCH v2 5/5] clk: rockchip: add clock controller for the RK3399 Xing Zheng
2016-03-08 23:34 ` Doug Anderson
[not found] ` <CAD=FV=VhMY=YO7zVYeP-+LY0gPvQ8yjaAUEGVJrMGLwbGjqVmg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-03-09 0:51 ` Jianqun Xu
2016-03-09 1:26 ` Xing Zheng
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