[PATCH 21/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588-nanopc-t6

Cristian Ciocaltea
2026-04-17T09:26:52Z

The board exposes the GPIO4_B1 and GPIO4_B2 lines to control the voltage
bias on the data lines for the HDMI0 and HDMI1 ports. These lines must
be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI
1.4/2.0 TMDS mode.

Wire up both HDMI ports to their respective GPIO lines using the
frl-enable-gpios property to allow adjusting the bias when transitioning
between TMDS and FRL operating modes.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
index 84b6b53f016a..be6f834264c7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
@@ -361,6 +361,9 @@ &gpu {
};

&hdmi0 {
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
status = "okay";
};

@@ -381,6 +384,9 @@ &hdmi0_sound {
};

&hdmi1 {
+ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
+ &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
status = "okay";
};

@@ -682,6 +688,16 @@ usr_led_pin: usr-led-pin {
};
};

+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ hdmi1_frl_en: hdmi1-frl-en {
+ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
hdmirx {
hdmirx_hpd: hdmirx-5v-detection {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;