Re: [PATCH v15 14/15] arm64: dts: rockchip: add NPU (RKNN) nodes to rk3576

From: "Heiko Stübner" <heiko@sntech.de>
To: tomeu@tomeuvizoso.net, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, joro@8bytes.org, will@kernel.org,
	robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de,
	ogabbay@kernel.org, zhangqing@rock-chips.com,
	Jiaxing Hu <gahing@gahingwoo.com>
Cc: royalnet026@gmail.com, abel.vesa@oss.qualcomm.com,
	sebastian.reichel@collabora.com, sidong.yang@furiosa.ai,
	u.kleine-koenig@baylibre.com, chaoyi.chen@rock-chips.com,
	diederik@cknow-tech.com, alchark@flipper.net, leonard@lausen.nl,
	jeff.hugo@oss.qualcomm.com, rfoss@kernel.org,
	dri-devel@lists.freedesktop.org,
	linux-rockchip@lists.infradead.org, iommu@lists.linux.dev,
	linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Jiaxing Hu <gahing@gahingwoo.com>,
	chaoyi.chen@rock-chips.com
Subject: Re: [PATCH v15 14/15] arm64: dts: rockchip: add NPU (RKNN) nodes to rk3576
Date: Wed, 04 Nov 2026 11:53:47 +0100	[thread overview]
Message-ID: <2915499.MsWZr2WtbB@diego> (raw)
In-Reply-To: <20261101082307.151957-15-gahing@gahingwoo.com>

Am Sonntag, 1. November 2026, 09:23:06 Mitteleuropäische Normalzeit schrieb Jiaxing Hu:
> Add the two RKNN cores and their IOMMUs, disabled, and label PD_NPU so a
> board can give it the NPU rail. Each core lists both core domains, its own
> first, as tested.
> 
> Assign CLK_RKNN_DSU0 594 MHz. Nothing in mainline sets its rate or the NPU
> rail, and at the 786 MHz it comes up at, on the 750 mV a ROCK 4D boots
> with, two cores running together write wrong words, 11 to 25 in each pass
> of 5400 rows. 594 MHz is clean, and Rockchip's OPP table asks only 725 mV
> of its 500 and 600 MHz steps.
> 
> Signed-off-by: Jiaxing Hu <gahing@gahingwoo.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3576.dtsi | 74 +++++++++++++++++++++++-
>  1 file changed, 73 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> index ea9229b6e6f5..80943d748bfa 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> @@ -1057,7 +1057,7 @@ power: power-controller {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
>  
> -				power-domain@RK3576_PD_NPU {
> +				pd_npu: power-domain@RK3576_PD_NPU {
>  					reg = <RK3576_PD_NPU>;
>  					#power-domain-cells = <1>;
>  					#address-cells = <1>;
> @@ -1284,6 +1284,78 @@ power-domain@RK3576_PD_VO1 {
>  			};
>  		};
>  
> +		rknn_core_0: npu@27700000 {
> +			compatible = "rockchip,rk3576-rknn-core";
> +			reg = <0x0 0x27700000 0x0 0x1000>,
> +			      <0x0 0x27701000 0x0 0x1000>,
> +			      <0x0 0x27703000 0x0 0x1000>;
> +			reg-names = "pc", "cna", "core";
> +			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cru ACLK_RKNN0>, <&cru HCLK_RKNN_ROOT>,
> +				 <&cru CLK_RKNN_DSU0>, <&cru PCLK_NPUTOP_ROOT>,
> +				 <&cru ACLK_RKNN_CBUF>, <&cru HCLK_RKNN_CBUF>;
> +			clock-names = "aclk", "hclk", "npu", "pclk",
> +				      "aclk_cbuf", "hclk_cbuf";
> +			assigned-clocks = <&cru CLK_RKNN_DSU0>;
> +			assigned-clock-rates = <594000000>;
> +			resets = <&cru SRST_A_RKNN0>;
> +			reset-names = "srst_a";
> +			power-domains = <&power RK3576_PD_NPU0>, <&power RK3576_PD_NPU1>;

Why do you need both power-domains here?
The naming does suggest each belongs to one core - similar to the rk3588?

If each core really needs both domains, please state this explicitly.

Rockchip sadly does not provide RKNN documentation the first
two parts of the TRM.

Heiko

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