Re: [PATCH v2 1/3] dt-bindings: gpio: rockchip,gpio-bank: Add rockchip,grf property

["Heiko Stübner" <heiko@sntech.de>]

Am Dienstag, 21. Juli 2026, 10:13:38 Mitteleuropäische Sommerzeit schrieb Krzysztof Kozlowski:
> On Tue, Jul 14, 2026 at 01:25:29PM -0600, Simon Glass wrote:
> > Some Rockchip SoCs, such as the RV1106, give each GPIO bank its own
> > IO control (IOC) register block rather than grouping the registers of
> > all banks into a shared GRF region. Add an optional rockchip,grf
> > property to the gpio-bank binding so that each bank node can reference
> > the syscon for its own IOC block.
> > 
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> > 
> > Changes in v2:
> > - Add new patch for the per-bank IOC reference
> > 
> >  .../devicetree/bindings/gpio/rockchip,gpio-bank.yaml       | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
> > index bdd83f42615c..774e9c7de606 100644
> > --- a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
> > +++ b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
> > @@ -44,6 +44,13 @@ properties:
> >    power-domains:
> >      maxItems: 1
> >  
> > +  rockchip,grf:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description:
> > +      The phandle of the syscon node managing the IO control registers
> > +      of this bank, on SoCs such as the RV1106 where each GPIO bank has
> > +      its own IOC block.
> 
> I do not see usage of it in patchset linked in cover letter with DTS.
> 
> I have doubts that whil having one GRF region you have GPIO banks
> pointing to different GRF regions.
> 
> It's possible if you would have multiple GRFs, but you do not. You have
> one GRF, right?

per my reply to the grf binding patch, Rockchip invented yet another way
to describe their pin-config - in completely separate blocks strewn accross
the whole io-space this time.

So describing the associated pinconfig grf per bank, does sound pretty
nice for that problem.

In the early beginning Rockchip had one really big GRF for all of those
settings bits - which included the iomux settings.
Later on they moved _parts_ of that to another big GRF that still wasn't
dedicated to pin-config.
Recently pin-config got its own GRF - for all pins
And now it seems we're at one GRF per pinbank ;-) .

When I asked some years ago - when there even was usbphy control in here
(and those regs+bits also moved all the time), the _paraphrased_ answer
was "because hardware-designers find it nicer" ;-) .


Heiko



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