* [PATCH] mmc: dw_mmc-rockchip: Fix wrong internal phase calculate
@ 2025-11-04 3:51 Shawn Lin
2025-11-06 23:02 ` Heiko Stuebner
2025-11-11 17:36 ` Ulf Hansson
0 siblings, 2 replies; 3+ messages in thread
From: Shawn Lin @ 2025-11-04 3:51 UTC (permalink / raw)
To: Ulf Hansson
Cc: linux-rockchip, Heiko Stuebner, Detlev Casanova, linux-mmc,
Shawn Lin
ciu clock is 2 times of io clock, but the sample clk used is
derived from io clock provided to the card. So we should use
io clock to calculate the phase.
Fixes: 59903441f5e4 ("mmc: dw_mmc-rockchip: Add internal phase support")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/mmc/host/dw_mmc-rockchip.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
index 82dd906..6813549 100644
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
@@ -42,7 +42,7 @@ struct dw_mci_rockchip_priv_data {
*/
static int rockchip_mmc_get_internal_phase(struct dw_mci *host, bool sample)
{
- unsigned long rate = clk_get_rate(host->ciu_clk);
+ unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
u32 raw_value;
u16 degrees;
u32 delay_num = 0;
@@ -85,7 +85,7 @@ static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample)
static int rockchip_mmc_set_internal_phase(struct dw_mci *host, bool sample, int degrees)
{
- unsigned long rate = clk_get_rate(host->ciu_clk);
+ unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
u8 nineties, remainder;
u8 delay_num;
u32 raw_value;
--
2.7.4
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] mmc: dw_mmc-rockchip: Fix wrong internal phase calculate
2025-11-04 3:51 [PATCH] mmc: dw_mmc-rockchip: Fix wrong internal phase calculate Shawn Lin
@ 2025-11-06 23:02 ` Heiko Stuebner
2025-11-11 17:36 ` Ulf Hansson
1 sibling, 0 replies; 3+ messages in thread
From: Heiko Stuebner @ 2025-11-06 23:02 UTC (permalink / raw)
To: Ulf Hansson, Shawn Lin
Cc: linux-rockchip, Detlev Casanova, linux-mmc, Shawn Lin
Am Dienstag, 4. November 2025, 04:51:23 Mitteleuropäische Normalzeit schrieb Shawn Lin:
> ciu clock is 2 times of io clock, but the sample clk used is
> derived from io clock provided to the card. So we should use
> io clock to calculate the phase.
>
> Fixes: 59903441f5e4 ("mmc: dw_mmc-rockchip: Add internal phase support")
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
> ---
>
> drivers/mmc/host/dw_mmc-rockchip.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
> index 82dd906..6813549 100644
> --- a/drivers/mmc/host/dw_mmc-rockchip.c
> +++ b/drivers/mmc/host/dw_mmc-rockchip.c
> @@ -42,7 +42,7 @@ struct dw_mci_rockchip_priv_data {
> */
> static int rockchip_mmc_get_internal_phase(struct dw_mci *host, bool sample)
> {
> - unsigned long rate = clk_get_rate(host->ciu_clk);
> + unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
> u32 raw_value;
> u16 degrees;
> u32 delay_num = 0;
> @@ -85,7 +85,7 @@ static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample)
>
> static int rockchip_mmc_set_internal_phase(struct dw_mci *host, bool sample, int degrees)
> {
> - unsigned long rate = clk_get_rate(host->ciu_clk);
> + unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
> u8 nineties, remainder;
> u8 delay_num;
> u32 raw_value;
>
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^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] mmc: dw_mmc-rockchip: Fix wrong internal phase calculate
2025-11-04 3:51 [PATCH] mmc: dw_mmc-rockchip: Fix wrong internal phase calculate Shawn Lin
2025-11-06 23:02 ` Heiko Stuebner
@ 2025-11-11 17:36 ` Ulf Hansson
1 sibling, 0 replies; 3+ messages in thread
From: Ulf Hansson @ 2025-11-11 17:36 UTC (permalink / raw)
To: Shawn Lin; +Cc: linux-rockchip, Heiko Stuebner, Detlev Casanova, linux-mmc
On Tue, 4 Nov 2025 at 04:51, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>
> ciu clock is 2 times of io clock, but the sample clk used is
> derived from io clock provided to the card. So we should use
> io clock to calculate the phase.
>
> Fixes: 59903441f5e4 ("mmc: dw_mmc-rockchip: Add internal phase support")
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Applied for fixes and by adding a stable-tag, thanks!
Kind regards
Uffe
> ---
>
> drivers/mmc/host/dw_mmc-rockchip.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
> index 82dd906..6813549 100644
> --- a/drivers/mmc/host/dw_mmc-rockchip.c
> +++ b/drivers/mmc/host/dw_mmc-rockchip.c
> @@ -42,7 +42,7 @@ struct dw_mci_rockchip_priv_data {
> */
> static int rockchip_mmc_get_internal_phase(struct dw_mci *host, bool sample)
> {
> - unsigned long rate = clk_get_rate(host->ciu_clk);
> + unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
> u32 raw_value;
> u16 degrees;
> u32 delay_num = 0;
> @@ -85,7 +85,7 @@ static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample)
>
> static int rockchip_mmc_set_internal_phase(struct dw_mci *host, bool sample, int degrees)
> {
> - unsigned long rate = clk_get_rate(host->ciu_clk);
> + unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
> u8 nineties, remainder;
> u8 delay_num;
> u32 raw_value;
> --
> 2.7.4
>
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-11-04 3:51 [PATCH] mmc: dw_mmc-rockchip: Fix wrong internal phase calculate Shawn Lin
2025-11-06 23:02 ` Heiko Stuebner
2025-11-11 17:36 ` Ulf Hansson
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