[PATCH v1 0/5] Add eFuse driver of Rockchip SoC

[PATCH v1 0/5] Add eFuse driver of Rockchip SoC

[Shunqian Zheng]

From: ZhengShunQian <zhengsq@rock-chips.com>

Base on nvmem framework, this series patches
implement the eFuse driver of Rockchip SoC.
The data from eFuse contains CPU leakage, chip code and version etc.

The flow of reading data from eFuse is quite simple,
configure the CTRL register, write data address to CTRL
register, then data is available in DOUT register.

The changes versus V0:
  1. Enable/disable clock when required.
  2. Split the drivers patch into three patches.
  3. Update the docs of eFuse.

ZhengShunQian (5):
  clk: rockchip: rk3288: Add the clock id of eFuse
  nvmem: fix the out-of-range leak in read/write()
  nvmem: rockchip-efuse: implement efuse driver
  Documentation: rockchip-efuse: describe the usage of eFuse
  ARM: dts: rockchip: add eFuse config of rk3288 SoC

 .../devicetree/bindings/nvmem/rockchip-efuse.txt   |  38 ++++
 arch/arm/boot/dts/rk3288.dtsi                      |  13 ++
 drivers/clk/rockchip/clk-rk3288.c                  |   2 +-
 drivers/nvmem/Kconfig                              |  10 ++
 drivers/nvmem/Makefile                             |   2 +
 drivers/nvmem/core.c                               |   4 +-
 drivers/nvmem/rockchip-efuse.c                     | 193 +++++++++++++++++++++
 include/dt-bindings/clock/rk3288-cru.h             |   1 +
 8 files changed, 260 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
 create mode 100644 drivers/nvmem/rockchip-efuse.c

-- 
1.9.1

[PATCH v1 1/5] clk: rockchip: rk3288: Add the clock id of eFuse

[Shunqian Zheng]

From: ZhengShunQian <zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

The clock id is necessary item, changing it from 0
then can be referred in driver and device tree.

Signed-off-by: ZhengShunQian <zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
 drivers/clk/rockchip/clk-rk3288.c      | 2 +-
 include/dt-bindings/clock/rk3288-cru.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 0df5bae..31c4f78 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -647,7 +647,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 	GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
 	GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
 	GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
-	GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
+	GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
 	GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
 
 	/* ddrctrl [DDR Controller PHY clock] gates */
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index c719aac..ab74d5e 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -164,6 +164,7 @@
 #define PCLK_DDRUPCTL1		366
 #define PCLK_PUBL1		367
 #define PCLK_WDT		368
+#define PCLK_EFUSE256		369
 
 /* hclk gates */
 #define HCLK_GPS		448
-- 
1.9.1

[PATCH v1 2/5] nvmem: fix the out-of-range leak in read/write()

[Shunqian Zheng]

From: ZhengShunQian <zhengsq@rock-chips.com>

The position to read/write must be less than max
register size.

Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 drivers/nvmem/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c
index d3c6676..f4af8e5 100644
--- a/drivers/nvmem/core.c
+++ b/drivers/nvmem/core.c
@@ -67,7 +67,7 @@ static ssize_t bin_attr_nvmem_read(struct file *filp, struct kobject *kobj,
 	int rc;
 
 	/* Stop the user from reading */
-	if (pos > nvmem->size)
+	if (pos >= nvmem->size)
 		return 0;
 
 	if (pos + count > nvmem->size)
@@ -92,7 +92,7 @@ static ssize_t bin_attr_nvmem_write(struct file *filp, struct kobject *kobj,
 	int rc;
 
 	/* Stop the user from writing */
-	if (pos > nvmem->size)
+	if (pos >= nvmem->size)
 		return 0;
 
 	if (pos + count > nvmem->size)
-- 
1.9.1

[PATCH v1 3/5] nvmem: rockchip-efuse: implement efuse driver

[Shunqian Zheng]

From: ZhengShunQian <zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

There are some SoC specified values store in eFuse,
such as the cpu_leakage and cpu_version,
this driver can expose these values to /sys base on nvmem.

Signed-off-by: Caesar Wang <caesar.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: ZhengShunQian <zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
 drivers/nvmem/Kconfig          |  10 +++
 drivers/nvmem/Makefile         |   2 +
 drivers/nvmem/rockchip-efuse.c | 193 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 205 insertions(+)
 create mode 100644 drivers/nvmem/rockchip-efuse.c

diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 8db2978..98f1fac 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -36,4 +36,14 @@ config NVMEM_SUNXI_SID
 	  This driver can also be built as a module. If so, the module
 	  will be called nvmem_sunxi_sid.
 
+config ROCKCHIP_EFUSE
+	tristate "Rockchip eFuse Support"
+	depends on ARCH_ROCKCHIP || COMPILE_TEST
+	help
+	  This is a simple drive to dump specified values of Rockchip SoC
+	  from eFuse, such as cpu-leakage.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called nvmem_rockchip_efuse.
+
 endif
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 4328b93..093a528 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -10,3 +10,5 @@ obj-$(CONFIG_QCOM_QFPROM)	+= nvmem_qfprom.o
 nvmem_qfprom-y			:= qfprom.o
 obj-$(CONFIG_NVMEM_SUNXI_SID)	+= nvmem_sunxi_sid.o
 nvmem_sunxi_sid-y		:= sunxi_sid.o
+obj-$(CONFIG_ROCKCHIP_EFUSE)	+= nvmem_rockchip_efuse.o
+nvmem_rockchip_efuse-y		:= rockchip-efuse.o
diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
new file mode 100644
index 0000000..9d1e2e0
--- /dev/null
+++ b/drivers/nvmem/rockchip-efuse.c
@@ -0,0 +1,193 @@
+/*
+ * Rockchip eFuse Driver
+ *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/nvmem-provider.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+
+#define EFUSE_A_SHIFT			6
+#define EFUSE_A_MASK			0x3ff
+#define EFUSE_PGENB			BIT(3)
+#define EFUSE_LOAD			BIT(2)
+#define EFUSE_STROBE			BIT(1)
+#define EFUSE_CSB			BIT(0)
+
+#define REG_EFUSE_CTRL			0x0000
+#define REG_EFUSE_DOUT			0x0004
+
+struct rockchip_efuse_context {
+	struct device *dev;
+	void __iomem *base;
+	struct clk *efuse_clk;
+};
+
+static int rockchip_efuse_write(void *context, const void *data, size_t count)
+{
+	/* Nothing TBD, Read-Only */
+	return 0;
+}
+
+static int rockchip_efuse_read(void *context,
+			       const void *reg, size_t reg_size,
+			       void *val, size_t val_size)
+{
+	unsigned int offset = *(u32 *)reg;
+	struct rockchip_efuse_context *_context = context;
+	void __iomem *base = _context->base;
+	struct clk *clk = _context->efuse_clk;
+	u8 *buf = val;
+	int ret;
+
+	ret = clk_prepare(clk);
+	if (ret < 0) {
+		dev_err(_context->dev, "failed to prepare efuse clk\n");
+		return ret;
+	}
+	ret = clk_enable(clk);
+	if (ret < 0) {
+		dev_err(_context->dev, "failed to enable efuse clk\n");
+		clk_unprepare(clk);
+		return ret;
+	}
+
+	writel(EFUSE_LOAD | EFUSE_PGENB, base + REG_EFUSE_CTRL);
+	udelay(1);
+	while (val_size) {
+		writel(readl(base + REG_EFUSE_CTRL) &
+			     (~(EFUSE_A_MASK << EFUSE_A_SHIFT)),
+			     base + REG_EFUSE_CTRL);
+		writel(readl(base + REG_EFUSE_CTRL) |
+			     ((offset & EFUSE_A_MASK) << EFUSE_A_SHIFT),
+			     base + REG_EFUSE_CTRL);
+		udelay(1);
+		writel(readl(base + REG_EFUSE_CTRL) |
+			     EFUSE_STROBE, base + REG_EFUSE_CTRL);
+		udelay(1);
+		*buf++ = readb(base + REG_EFUSE_DOUT);
+		writel(readl(base + REG_EFUSE_CTRL) &
+		     (~EFUSE_STROBE), base + REG_EFUSE_CTRL);
+		udelay(1);
+
+		val_size -= 1;
+		offset += 1;
+	}
+
+	/* Switch to standby mode */
+	writel(EFUSE_PGENB | EFUSE_CSB, base + REG_EFUSE_CTRL);
+
+	clk_disable(clk);
+	clk_unprepare(clk);
+
+	return 0;
+}
+
+static struct regmap_bus rockchip_efuse_bus = {
+	.read = rockchip_efuse_read,
+	.write = rockchip_efuse_write,
+	.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
+	.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
+};
+
+struct regmap_config rockchip_efuse_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 1,
+	.val_bits = 8,
+};
+
+static struct nvmem_config econfig = {
+	.name = "rockchip-efuse",
+	.owner = THIS_MODULE,
+	.read_only = true,
+};
+
+static const struct of_device_id rockchip_efuse_match[] = {
+	{ .compatible = "rockchip,rockchip-efuse",},
+	{ /* sentinel */},
+};
+MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
+
+int rockchip_efuse_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct nvmem_device *nvmem;
+	struct regmap *regmap;
+	void __iomem *base;
+	struct clk *clk;
+	struct rockchip_efuse_context *context;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	context = devm_kzalloc(dev, sizeof(struct rockchip_efuse_context),
+			       GFP_KERNEL);
+	if (IS_ERR(context))
+		return PTR_ERR(context);
+
+	clk = devm_clk_get(dev, "pclk_efuse");
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	context->dev = dev;
+	context->base = base;
+	context->efuse_clk = clk;
+
+	rockchip_efuse_regmap_config.max_register = resource_size(res) - 1;
+
+	regmap = devm_regmap_init(dev, &rockchip_efuse_bus,
+				  context, &rockchip_efuse_regmap_config);
+	if (IS_ERR(regmap)) {
+		dev_err(dev, "regmap init failed\n");
+		return PTR_ERR(regmap);
+	}
+	econfig.dev = dev;
+	nvmem = nvmem_register(&econfig);
+	if (IS_ERR(nvmem))
+		return PTR_ERR(nvmem);
+
+	platform_set_drvdata(pdev, nvmem);
+
+	return 0;
+}
+
+int rockchip_efuse_remove(struct platform_device *pdev)
+{
+	struct nvmem_device *nvmem = platform_get_drvdata(pdev);
+
+	return nvmem_unregister(nvmem);
+}
+
+static struct platform_driver rockchip_efuse_driver = {
+	.probe = rockchip_efuse_probe,
+	.remove = rockchip_efuse_remove,
+	.driver = {
+		.name = "rockchip-efuse",
+		.of_match_table = rockchip_efuse_match,
+	},
+};
+
+module_platform_driver(rockchip_efuse_driver);
+MODULE_DESCRIPTION("rockchip_efuse driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

[PATCH v1 4/5] Documentation: rockchip-efuse: describe the usage of eFuse

[Shunqian Zheng]

From: ZhengShunQian <zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

This patch add the bindings document of rockchip eFuse driver.

Signed-off-by: ZhengShunQian <zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
 .../devicetree/bindings/nvmem/rockchip-efuse.txt   | 38 ++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt

diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
new file mode 100644
index 0000000..8f86ab3
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
@@ -0,0 +1,38 @@
+= Rockchip eFuse device tree bindings =
+
+Required properties:
+- compatible: Should be "rockchip,rockchip-efuse"
+- reg: Should contain the registers location and exact eFuse size
+- clocks: Should be the clock id of eFuse
+- clock-names: Should be "pclk_efuse"
+
+= Data cells =
+Are child nodes of eFuse, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+Example:
+
+	efuse: efuse@ffb40000 {
+		compatible = "rockchip,rockchip-efuse";
+		reg = <0xffb40000 0x20>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clocks = <&cru PCLK_EFUSE256>;
+		clock-names = "pclk_efuse";
+
+		/* Data cells */
+		cpu_leakage: cpu_leakage {
+			reg = <0x17 0x1>;
+		};
+	};
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+Example:
+
+	cpu_leakage {
+		...
+		nvmem-cells = <&cpu_leakage>;
+		nvmem-cell-names = "cpu_leakage";
+	};
-- 
1.9.1

[PATCH v1 5/5] ARM: dts: rockchip: add eFuse config of rk3288 SoC

[Shunqian Zheng]

From: ZhengShunQian <zhengsq@rock-chips.com>

This patch add the eFuse dt config of rk3288 SoC.

Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
---
 arch/arm/boot/dts/rk3288.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 2db91c9..4632e0d 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -749,6 +749,19 @@
 		interrupts = <GIC_PPI 9 0xf04>;
 	};
 
+	efuse: efuse@ffb40000 {
+		compatible = "rockchip,rockchip-efuse";
+		reg = <0xffb40000 0x20>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clocks = <&cru PCLK_EFUSE256>;
+		clock-names = "pclk_efuse";
+
+		cpu_leakage: cpu_leakage {
+			reg = <0x17 0x1>;
+		};
+	};
+
 	usbphy: phy {
 		compatible = "rockchip,rk3288-usb-phy";
 		rockchip,grf = <&grf>;
-- 
1.9.1

Re: [PATCH v1 1/5] clk: rockchip: rk3288: Add the clock id of eFuse

[Heiko Stübner]

Am Dienstag, 11. August 2015, 14:15:02 schrieb Shunqian Zheng:
> From: ZhengShunQian <zhengsq@rock-chips.com>
> 
> The clock id is necessary item, changing it from 0
> then can be referred in driver and device tree.
> 
> Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>


Patch is missing the clock maintainers and list
Mike Turquette <mturquette@baylibre.com>
Stephen Boyd <sboyd@codeaurora.org>
linux-clk@vger.kernel.org


> ---
>  drivers/clk/rockchip/clk-rk3288.c      | 2 +-
>  include/dt-bindings/clock/rk3288-cru.h | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3288.c
> b/drivers/clk/rockchip/clk-rk3288.c index 0df5bae..31c4f78 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -647,7 +647,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
> __initdata = { GATE(0, "pclk_efuse_1024", "pclk_cpu", 0,
> RK3288_CLKGATE_CON(11), 2, GFLAGS),

out of curiosity, as I haven't found anything about it yet, do you also know 
what the pclk_efuse_1024 is used for?


Heiko

> GATE(PCLK_TZPC, "pclk_tzpc",
> "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), GATE(PCLK_UART2,
> "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), -	GATE(0,
> "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
> +	GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0,
> RK3288_CLKGATE_CON(11), 10, GFLAGS), GATE(PCLK_RKPWM, "pclk_rkpwm",
> "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
> 
>  	/* ddrctrl [DDR Controller PHY clock] gates */
> diff --git a/include/dt-bindings/clock/rk3288-cru.h
> b/include/dt-bindings/clock/rk3288-cru.h index c719aac..ab74d5e 100644
> --- a/include/dt-bindings/clock/rk3288-cru.h
> +++ b/include/dt-bindings/clock/rk3288-cru.h
> @@ -164,6 +164,7 @@
>  #define PCLK_DDRUPCTL1		366
>  #define PCLK_PUBL1		367
>  #define PCLK_WDT		368
> +#define PCLK_EFUSE256		369
> 
>  /* hclk gates */
>  #define HCLK_GPS		448

Re: [PATCH v1 1/5] clk: rockchip: rk3288: Add the clock id of eFuse

[Heiko Stübner]

Am Dienstag, 11. August 2015, 09:16:32 schrieb Heiko Stübner:
> Am Dienstag, 11. August 2015, 14:15:02 schrieb Shunqian Zheng:
> > From: ZhengShunQian <zhengsq@rock-chips.com>
> > 
> > The clock id is necessary item, changing it from 0
> > then can be referred in driver and device tree.
> > 
> > Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
> 
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> 
> 
> Patch is missing the clock maintainers and list
> Mike Turquette <mturquette@baylibre.com>
> Stephen Boyd <sboyd@codeaurora.org>
> linux-clk@vger.kernel.org
> 
> > ---
> > 
> >  drivers/clk/rockchip/clk-rk3288.c      | 2 +-
> >  include/dt-bindings/clock/rk3288-cru.h | 1 +
> >  2 files changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/rockchip/clk-rk3288.c
> > b/drivers/clk/rockchip/clk-rk3288.c index 0df5bae..31c4f78 100644
> > --- a/drivers/clk/rockchip/clk-rk3288.c
> > +++ b/drivers/clk/rockchip/clk-rk3288.c
> > @@ -647,7 +647,7 @@ static struct rockchip_clk_branch
> > rk3288_clk_branches[]
> > __initdata = { GATE(0, "pclk_efuse_1024", "pclk_cpu", 0,
> > RK3288_CLKGATE_CON(11), 2, GFLAGS),
> 
> out of curiosity, as I haven't found anything about it yet, do you also know
> what the pclk_efuse_1024 is used for?

ok, found this myself (the 32x32 bit efuse), but it looks like there is also a 
clock "acc_efuse" - what is this used for?


Heiko

> 
> > GATE(PCLK_TZPC, "pclk_tzpc",
> > "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), GATE(PCLK_UART2,
> > "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), -	
GATE(0,
> > "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
> > +	GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0,
> > RK3288_CLKGATE_CON(11), 10, GFLAGS), GATE(PCLK_RKPWM, "pclk_rkpwm",
> > "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
> > 
> >  	/* ddrctrl [DDR Controller PHY clock] gates */
> > 
> > diff --git a/include/dt-bindings/clock/rk3288-cru.h
> > b/include/dt-bindings/clock/rk3288-cru.h index c719aac..ab74d5e 100644
> > --- a/include/dt-bindings/clock/rk3288-cru.h
> > +++ b/include/dt-bindings/clock/rk3288-cru.h
> > @@ -164,6 +164,7 @@
> > 
> >  #define PCLK_DDRUPCTL1		366
> >  #define PCLK_PUBL1		367
> >  #define PCLK_WDT		368
> > 
> > +#define PCLK_EFUSE256		369
> > 
> >  /* hclk gates */
> >  #define HCLK_GPS		448

Re: [PATCH v1 1/5] clk: rockchip: rk3288: Add the clock id of eFuse

[Shunqian Zheng]

On 2015年08月11日 15:16, Heiko Stübner wrote:
> Am Dienstag, 11. August 2015, 14:15:02 schrieb Shunqian Zheng:
>> From: ZhengShunQian <zhengsq@rock-chips.com>
>>
>> The clock id is necessary item, changing it from 0
>> then can be referred in driver and device tree.
>>
>> Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
>
>
> Patch is missing the clock maintainers and list
> Mike Turquette <mturquette@baylibre.com>
> Stephen Boyd <sboyd@codeaurora.org>
> linux-clk@vger.kernel.org
>
>
>> ---
>>   drivers/clk/rockchip/clk-rk3288.c      | 2 +-
>>   include/dt-bindings/clock/rk3288-cru.h | 1 +
>>   2 files changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/rockchip/clk-rk3288.c
>> b/drivers/clk/rockchip/clk-rk3288.c index 0df5bae..31c4f78 100644
>> --- a/drivers/clk/rockchip/clk-rk3288.c
>> +++ b/drivers/clk/rockchip/clk-rk3288.c
>> @@ -647,7 +647,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
>> __initdata = { GATE(0, "pclk_efuse_1024", "pclk_cpu", 0,
>> RK3288_CLKGATE_CON(11), 2, GFLAGS),
> out of curiosity, as I haven't found anything about it yet, do you also know
> what the pclk_efuse_1024 is used for?
>
>
> Heiko
As I known, the other efuse(efuse_1024) is only used for internal.

Thank you !!

Shunqian
>> GATE(PCLK_TZPC, "pclk_tzpc",
>> "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), GATE(PCLK_UART2,
>> "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), -	GATE(0,
>> "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
>> +	GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0,
>> RK3288_CLKGATE_CON(11), 10, GFLAGS), GATE(PCLK_RKPWM, "pclk_rkpwm",
>> "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
>>
>>   	/* ddrctrl [DDR Controller PHY clock] gates */
>> diff --git a/include/dt-bindings/clock/rk3288-cru.h
>> b/include/dt-bindings/clock/rk3288-cru.h index c719aac..ab74d5e 100644
>> --- a/include/dt-bindings/clock/rk3288-cru.h
>> +++ b/include/dt-bindings/clock/rk3288-cru.h
>> @@ -164,6 +164,7 @@
>>   #define PCLK_DDRUPCTL1		366
>>   #define PCLK_PUBL1		367
>>   #define PCLK_WDT		368
>> +#define PCLK_EFUSE256		369
>>
>>   /* hclk gates */
>>   #define HCLK_GPS		448
>
>
>

Re: [PATCH v1 1/5] clk: rockchip: rk3288: Add the clock id of eFuse

[Shunqian Zheng]

Heiko,

On 2015年08月11日 15:22, Heiko Stübner wrote:
> Am Dienstag, 11. August 2015, 09:16:32 schrieb Heiko Stübner:
>> Am Dienstag, 11. August 2015, 14:15:02 schrieb Shunqian Zheng:
>>> From: ZhengShunQian <zhengsq@rock-chips.com>
>>>
>>> The clock id is necessary item, changing it from 0
>>> then can be referred in driver and device tree.
>>>
>>> Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
>> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
>>
>>
>> Patch is missing the clock maintainers and list
>> Mike Turquette <mturquette@baylibre.com>
>> Stephen Boyd <sboyd@codeaurora.org>
>> linux-clk@vger.kernel.org
I will re-send this patch and cc to clock maintainers later...
>>
>>> ---
>>>
>>>   drivers/clk/rockchip/clk-rk3288.c      | 2 +-
>>>   include/dt-bindings/clock/rk3288-cru.h | 1 +
>>>   2 files changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/rockchip/clk-rk3288.c
>>> b/drivers/clk/rockchip/clk-rk3288.c index 0df5bae..31c4f78 100644
>>> --- a/drivers/clk/rockchip/clk-rk3288.c
>>> +++ b/drivers/clk/rockchip/clk-rk3288.c
>>> @@ -647,7 +647,7 @@ static struct rockchip_clk_branch
>>> rk3288_clk_branches[]
>>> __initdata = { GATE(0, "pclk_efuse_1024", "pclk_cpu", 0,
>>> RK3288_CLKGATE_CON(11), 2, GFLAGS),
>> out of curiosity, as I haven't found anything about it yet, do you also know
>> what the pclk_efuse_1024 is used for?
> ok, found this myself (the 32x32 bit efuse), but it looks like there is also a
> clock "acc_efuse" - what is this used for?
Sorry, I have not idea too..
>
>
> Heiko
>
>>> GATE(PCLK_TZPC, "pclk_tzpc",
>>> "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), GATE(PCLK_UART2,
>>> "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), -	
> GATE(0,
>>> "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
>>> +	GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0,
>>> RK3288_CLKGATE_CON(11), 10, GFLAGS), GATE(PCLK_RKPWM, "pclk_rkpwm",
>>> "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
>>>
>>>   	/* ddrctrl [DDR Controller PHY clock] gates */
>>>
>>> diff --git a/include/dt-bindings/clock/rk3288-cru.h
>>> b/include/dt-bindings/clock/rk3288-cru.h index c719aac..ab74d5e 100644
>>> --- a/include/dt-bindings/clock/rk3288-cru.h
>>> +++ b/include/dt-bindings/clock/rk3288-cru.h
>>> @@ -164,6 +164,7 @@
>>>
>>>   #define PCLK_DDRUPCTL1		366
>>>   #define PCLK_PUBL1		367
>>>   #define PCLK_WDT		368
>>>
>>> +#define PCLK_EFUSE256		369
>>>
>>>   /* hclk gates */
>>>   #define HCLK_GPS		448
>
>
>



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Re: [PATCH v1 3/5] nvmem: rockchip-efuse: implement efuse driver

[Srinivas Kandagatla]

On 11/08/15 07:15, Shunqian Zheng wrote:
> From: ZhengShunQian <zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>
> There are some SoC specified values store in eFuse,
> such as the cpu_leakage and cpu_version,
> this driver can expose these values to /sys base on nvmem.
>
> Signed-off-by: Caesar Wang <caesar.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: ZhengShunQian <zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
>   drivers/nvmem/Kconfig          |  10 +++
>   drivers/nvmem/Makefile         |   2 +
>   drivers/nvmem/rockchip-efuse.c | 193 +++++++++++++++++++++++++++++++++++++++++
>   3 files changed, 205 insertions(+)
>   create mode 100644 drivers/nvmem/rockchip-efuse.c
>
> diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> index 8db2978..98f1fac 100644
> --- a/drivers/nvmem/Kconfig
> +++ b/drivers/nvmem/Kconfig
> @@ -36,4 +36,14 @@ config NVMEM_SUNXI_SID
>   	  This driver can also be built as a module. If so, the module
>   	  will be called nvmem_sunxi_sid.
>
> +config ROCKCHIP_EFUSE
> +	tristate "Rockchip eFuse Support"
> +	depends on ARCH_ROCKCHIP || COMPILE_TEST
> +	help
> +	  This is a simple drive to dump specified values of Rockchip SoC
> +	  from eFuse, such as cpu-leakage.
> +
> +	  This driver can also be built as a module. If so, the module
> +	  will be called nvmem_rockchip_efuse.
> +
>   endif
> diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
> index 4328b93..093a528 100644
> --- a/drivers/nvmem/Makefile
> +++ b/drivers/nvmem/Makefile
> @@ -10,3 +10,5 @@ obj-$(CONFIG_QCOM_QFPROM)	+= nvmem_qfprom.o
>   nvmem_qfprom-y			:= qfprom.o
>   obj-$(CONFIG_NVMEM_SUNXI_SID)	+= nvmem_sunxi_sid.o
>   nvmem_sunxi_sid-y		:= sunxi_sid.o
> +obj-$(CONFIG_ROCKCHIP_EFUSE)	+= nvmem_rockchip_efuse.o
> +nvmem_rockchip_efuse-y		:= rockchip-efuse.o
> diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
> new file mode 100644
> index 0000000..9d1e2e0
> --- /dev/null
> +++ b/drivers/nvmem/rockchip-efuse.c
> @@ -0,0 +1,193 @@
> +/*
> + * Rockchip eFuse Driver
> + *
> + * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
> + * Author: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of version 2 of the GNU General Public License as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +
> +#include <linux/platform_device.h>
> +#include <linux/nvmem-provider.h>
> +#include <linux/slab.h>
> +#include <linux/regmap.h>
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/delay.h>
> +#include <linux/of.h>
> +#include <linux/clk.h>
> +
> +#define EFUSE_A_SHIFT			6
> +#define EFUSE_A_MASK			0x3ff
> +#define EFUSE_PGENB			BIT(3)
> +#define EFUSE_LOAD			BIT(2)
> +#define EFUSE_STROBE			BIT(1)
> +#define EFUSE_CSB			BIT(0)
> +
> +#define REG_EFUSE_CTRL			0x0000
> +#define REG_EFUSE_DOUT			0x0004
> +
> +struct rockchip_efuse_context {
> +	struct device *dev;
> +	void __iomem *base;
> +	struct clk *efuse_clk;
> +};
> +
> +static int rockchip_efuse_write(void *context, const void *data, size_t count)
> +{
> +	/* Nothing TBD, Read-Only */
> +	return 0;
> +}
> +
> +static int rockchip_efuse_read(void *context,
> +			       const void *reg, size_t reg_size,
> +			       void *val, size_t val_size)
> +{
> +	unsigned int offset = *(u32 *)reg;
> +	struct rockchip_efuse_context *_context = context;
> +	void __iomem *base = _context->base;
> +	struct clk *clk = _context->efuse_clk;
> +	u8 *buf = val;
> +	int ret;
> +
--snip--
> +	ret = clk_prepare(clk);
> +	if (ret < 0) {
> +		dev_err(_context->dev, "failed to prepare efuse clk\n");
> +		return ret;
> +	}
> +	ret = clk_enable(clk);
> +	if (ret < 0) {
> +		dev_err(_context->dev, "failed to enable efuse clk\n");
> +		clk_unprepare(clk);
> +		return ret;
> +	}
--snip--
can be replaced with

  clk_prepare_enable(clk);


> +
> +	writel(EFUSE_LOAD | EFUSE_PGENB, base + REG_EFUSE_CTRL);
> +	udelay(1);
> +	while (val_size) {
> +		writel(readl(base + REG_EFUSE_CTRL) &
> +			     (~(EFUSE_A_MASK << EFUSE_A_SHIFT)),
> +			     base + REG_EFUSE_CTRL);
> +		writel(readl(base + REG_EFUSE_CTRL) |
> +			     ((offset & EFUSE_A_MASK) << EFUSE_A_SHIFT),
> +			     base + REG_EFUSE_CTRL);
> +		udelay(1);
> +		writel(readl(base + REG_EFUSE_CTRL) |
> +			     EFUSE_STROBE, base + REG_EFUSE_CTRL);
> +		udelay(1);
> +		*buf++ = readb(base + REG_EFUSE_DOUT);
> +		writel(readl(base + REG_EFUSE_CTRL) &
> +		     (~EFUSE_STROBE), base + REG_EFUSE_CTRL);
> +		udelay(1);
> +
> +		val_size -= 1;
> +		offset += 1;
> +	}
> +
> +	/* Switch to standby mode */
> +	writel(EFUSE_PGENB | EFUSE_CSB, base + REG_EFUSE_CTRL);
> +
> +	clk_disable(clk);
> +	clk_unprepare(clk);
same replace it with

clk_disable_unprepare(clk);


Other than that the patch looks good to me.

with above fixed, you can add my Ack to this patch.

--srini

> +
> +	return 0;
> +}
> +