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From: Xing Zheng <zhengxing@rock-chips.com>
To: "Heiko Stübner" <heiko@sntech.de>
Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
	ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 5/9] dt-bindings: add documentation of rk3036 clock controller
Date: Thu, 24 Sep 2015 11:42:23 +0800	[thread overview]
Message-ID: <5603711F.3070809@rock-chips.com> (raw)
In-Reply-To: <14900712.fB7cIie92H@diego>

On 2015年09月17日 23:09, Heiko Stübner wrote:
> Am Donnerstag, 17. September 2015, 18:32:49 schrieb Xing Zheng:
>> Add the devicetree binding for the cru on the rk3036 which quite similar
>> structured as previous clock controllers.
>>
>> Signed-off-by: Xing Zheng<zhengxing@rock-chips.com>
>> ---
>>
>> Changes in v2: None
>>
>>   .../bindings/clock/rockchip,rk3036-cru.txt         |   60
>> ++++++++++++++++++++ 1 file changed, 60 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
>> b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt new file
>> mode 100644
>> index 0000000..ac3037a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
>> @@ -0,0 +1,60 @@
>> +* Rockchip RK3036 Clock and Reset Unit
>> +
>> +The RK3036 clock controller generates and supplies clock to various
>> +controllers within the SoC and also implements a reset controller for SoC
>> +peripherals.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be "rockchip,rk3036-cru"
>> +- reg: physical base address of the controller and length of memory mapped
>> +  region.
>> +- #clock-cells: should be 1.
>> +- #reset-cells: should be 1.
>> +
>> +Optional Properties:
>> +
>> +- rockchip,grf: phandle to the syscon managing the "general register files"
>> +  If missing pll rates are not changable, due to the missing pll lock
>> status. +
>> +Each clock is assigned an identifier and client nodes can use this
>> identifier +to specify the clock which they consume. All available clocks
>> are defined as +preprocessor macros in the dt-bindings/clock/rk3036-cru.h
>> headers and can be +used in device tree sources. Similar macros exist for
>> the reset sources in +these files.
>> +
>> +External clocks:
>> +
>> +There are several clocks that are generated outside the SoC. It is expected
>> +that they are defined using standard clock bindings with following
>> +clock-output-names:
>> + - "xin24m" - crystal input - required,
>> + - "xin32k" - rtc clock - optional,
> The rk3036 does not seem to use a rtc clock, so this should probably go away
Done.
>> + - "ext_i2s" - external I2S clock - optional,
>> + - "ext_hsadc" - external HSADC clock - optional,
>> + - "ext_vip" - external VIP clock - optional,
>> + - "ext_isp" - external ISP clock - optional,
>> + - "ext_jtag" - external JTAG clock - optional
> There do not seem to exist external clock sources for hsadc, vip, isp and jtag
> in your clock tree?
>
> missing here:
> - ext_gmac
Yes, done.
>> +
>> +Example: Clock controller node:
>> +
>> +	cru: cru@20000000 {
>> +		compatible = "rockchip,rk3036-cru";
>> +		reg =<0x20000000 0x1000>;
>> +		rockchip,grf =<&grf>;
>> +
>> +		#clock-cells =<1>;
>> +		#reset-cells =<1>;
>> +	};
>> +
>> +Example: UART controller node that consumes the clock generated by the
>> clock +  controller:
>> +
>> +	uart0: serial@20060000 {
>> +		compatible = "snps,dw-apb-uart";
>> +		reg =<0x20060000 0x100>;
>> +		interrupts =<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
>> +		reg-shift =<2>;
>> +		reg-io-width =<4>;
>> +		clocks =<&cru SCLK_UART0>;
>> +	};
Thanks.

  reply	other threads:[~2015-09-24  3:42 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-17  8:28 [PATCH v2 0/9] Build and support rk3036 SoC platform Xing Zheng
     [not found] ` <1442478540-15068-1-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2015-09-17  8:28   ` [PATCH v2 1/9] ARM: dts: rockchip: add core rk3036 dts Xing Zheng
2015-09-17  9:18     ` Heiko Stübner
2015-09-24  2:18       ` Xing Zheng
2015-09-17  8:28   ` [PATCH v2 2/9] clk: rockchip: add dt-binding header for rk3036 Xing Zheng
     [not found]     ` <1442478540-15068-3-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2015-09-17  9:25       ` Heiko Stübner
2015-09-24  2:17         ` Xing Zheng
2015-09-17  8:28   ` [PATCH v2 3/9] clk: rockchip: add clock controller " Xing Zheng
2015-09-17  9:47     ` Heiko Stübner
2015-09-24  3:04       ` Xing Zheng
2015-09-24  3:31         ` Xing Zheng
2015-10-07 10:24           ` Heiko Stuebner
2015-09-17  8:28   ` [PATCH v2 4/9] clk: rockchip: add new clock type and " Xing Zheng
     [not found]     ` <1442478540-15068-5-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2015-09-17  9:54       ` Heiko Stübner
2015-09-22 22:41     ` Stephen Boyd
2015-09-22 22:58       ` Heiko Stübner
2015-09-22 23:19         ` Stephen Boyd
2015-09-30 23:32           ` Heiko Stübner
2015-10-01  0:51             ` Stephen Boyd
2015-09-17 10:32   ` [PATCH v2 5/9] dt-bindings: add documentation of rk3036 clock controller Xing Zheng
     [not found]     ` <1442485969-1733-1-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2015-09-17 15:09       ` Heiko Stübner
2015-09-24  3:42         ` Xing Zheng [this message]
2015-09-17  9:59 ` [PATCH v2 0/9] Build and support rk3036 SoC platform Heiko Stübner
2015-09-17 10:34 ` [PATCH v2 6/9] pinctrl: rockchip: add support for the rk3036 Xing Zheng
2015-09-17 12:47   ` Heiko Stübner
2015-09-17 10:37 ` [PATCH v2 7/9] rockchip: make sure timer5 is enabled on rk3036 platforms Xing Zheng
2015-09-17 15:05   ` Heiko Stübner
2015-09-28 12:25     ` Xing Zheng
2015-09-28 12:44       ` Heiko Stübner
2015-09-28 12:53         ` Xing Zheng
2015-09-17 10:38 ` [PATCH v2 8/9] ARM: rockchip: add support smp for rk3036 Xing Zheng
2015-09-17 20:15   ` Heiko Stübner
2015-09-28 11:50     ` Xing Zheng

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