From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yakir Yang Subject: Re: [PATCH v8 11/17] dt-bindings: add document for rockchip dp phy Date: Sat, 31 Oct 2015 11:13:48 +0800 Message-ID: <563431EC.9050701@rock-chips.com> References: <1446020143-32645-1-git-send-email-ykk@rock-chips.com> <1446021068-11655-1-git-send-email-ykk@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Rob Herring Cc: Krzysztof Kozlowski , Heiko Stuebner , Seung-Woo Kim , Daniel Kurtz , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Andrzej Hajda , Gustavo Padovan , "linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Russell King , Joonyoung Shim , "open list:ARM/Rockchip SoC..." , Kishon Vijay Abraham I , Javier Martinez Canillas , Kukjin Kim , Thierry Reding , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Pawel Moll , Ian Campbell , Inki Dae , Sean Paul List-Id: linux-rockchip.vger.kernel.org On 10/31/2015 12:42 AM, Rob Herring wrote: > On Wed, Oct 28, 2015 at 3:31 AM, Yakir Yang wrote: >> Add dt binding documentation for rockchip display port PHY. >> >> Reviewed-by: Heiko Stuebner >> Signed-off-by: Yakir Yang > Acked-by: Rob Herring Thanks, - Yakir >> --- >> Changes in v8: >> - Remove the specific address in the example node name. (Heiko) >> >> Changes in v7: >> - Simplify the commit message. (Kishon) >> >> Changes in v6: None >> Changes in v5: >> - Split binding doc's from driver changes. (Rob) >> - Update the rockchip,grf explain in document, and correct the clock required >> elemets in document. (Rob & Heiko) >> >> Changes in v4: None >> Changes in v3: None >> Changes in v2: None >> >> .../devicetree/bindings/phy/rockchip-dp-phy.txt | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt >> >> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt >> new file mode 100644 >> index 0000000..00902cb >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt >> @@ -0,0 +1,22 @@ >> +Rockchip Soc Seroes Display Port PHY >> +------------------------------------ >> + >> +Required properties: >> +- compatible : should be one of the following supported values: >> + - "rockchip.rk3288-dp-phy" >> +- clocks: from common clock binding: handle to dp clock. >> + of memory mapped region. >> +- clock-names: from common clock binding: >> + Required elements: "24m" >> +- rockchip,grf: phandle to the syscon managing the "general register files" >> +- #phy-cells : from the generic PHY bindings, must be 0; >> + >> +Example: >> + >> +edp_phy: edp-phy { >> + compatible = "rockchip,rk3288-dp-phy"; >> + rockchip,grf = <&grf>; >> + clocks = <&cru SCLK_EDP_24M>; >> + clock-names = "24m"; >> + #phy-cells = <0>; >> +}; >> -- >> 1.9.1 >> >> > >