[PATCH 0/2] fix rk3066a-rayeager board hang when cpufreq changes

[PATCH 0/2] fix rk3066a-rayeager board hang when cpufreq changes

[Andy Yan]

I found the rayeager board always hang in the system boot
process or when cpufreq change. When check the BSP code[0]
from ChipSpark, I found the current vdd_arm voltage is too
low and so is the vdd_logic voltage, which should be modulated
by PWM3.

So I increase the vdd_arm voltage and enabled pwm3 as a pwm
regulator here.

[0] https://github.com/RockchipOpensourceCommunity/px2-android-kernel-3.0/blob/master/arch/arm/mach-rkpx2/board-rkpx2-sdk.c


Andy Yan (2):
  ARM: dts: rockchip: increase vdd_arm voltage for rk3066a-rayeager
    board
  ARM: dts: rockchip: enable pwm3 as pwm regulator for rk3066a-rayeager
    board

 arch/arm/boot/dts/rk3066a-rayeager.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

-- 
1.9.1


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[PATCH 1/2] ARM: dts: rockchip: increase vdd_arm voltage for rk3066a-rayeager board

[Andy Yan]

The current vdd_arm voltage is too low, increase it will make
the system more stable.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---

 arch/arm/boot/dts/rk3066a-rayeager.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
index 0bf6876..3d4c104 100644
--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -159,6 +159,14 @@
 
 &cpu0 {
 	cpu0-supply = <&vdd_arm>;
+	operating-points = <
+		/* kHz    uV */
+		1008000 1125000
+		816000  1125000
+		600000  1100000
+		504000  1100000
+		312000  1075000
+	>;
 };
 
 &emac {
-- 
1.9.1

[PATCH 2/2] ARM: dts: rockchip: enable pwm3 as pwm regulator for rk3066a-rayeager board

[Andy Yan]

Rayeager board use pwm3 modulate the vdd_logic voltage, so enable it.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---

 arch/arm/boot/dts/rk3066a-rayeager.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
index 3d4c104..d17a5b8 100644
--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -78,6 +78,18 @@
 		};
 	};
 
+	pwm_regulator: pwm-regulator {
+		compatible = "pwm-regulator";
+		pwms = <&pwm3 0 1000>;
+		regulator-name = "vdd_logic";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		voltage-table = <1000000 100>,
+				<1200000 42>;
+		status = "okay";
+	};
+
 	vsys: vsys-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vsys";
@@ -443,6 +455,10 @@
 	status = "okay";
 };
 
+&pwm3 {
+	status = "okay";
+};
+
 &saradc {
 	vref-supply = <&vcc_25>;
 	status = "okay";
-- 
1.9.1

Re: [PATCH 2/2] ARM: dts: rockchip: enable pwm3 as pwm regulator for rk3066a-rayeager board

[Heiko Stuebner]

Hi Andy,

Am Donnerstag, 14. Januar 2016, 20:35:56 schrieb Andy Yan:
> Rayeager board use pwm3 modulate the vdd_logic voltage, so enable it.
> 
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---
> 
>  arch/arm/boot/dts/rk3066a-rayeager.dts | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts
> b/arch/arm/boot/dts/rk3066a-rayeager.dts index 3d4c104..d17a5b8 100644
> --- a/arch/arm/boot/dts/rk3066a-rayeager.dts
> +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
> @@ -78,6 +78,18 @@
>  		};
>  	};
> 
> +	pwm_regulator: pwm-regulator {
> +		compatible = "pwm-regulator";
> +		pwms = <&pwm3 0 1000>;
> +		regulator-name = "vdd_logic";
> +		regulator-min-microvolt = <1200000>;
> +		regulator-max-microvolt = <1200000>;

I guess this is to make sure it stays at 1.2V at all times, or is the min-
microvolt settings supposed to be lower?


Thanks
Heiko

Re: [PATCH 1/2] ARM: dts: rockchip: increase vdd_arm voltage for rk3066a-rayeager board

[Heiko Stuebner]

Hi Andy,

Am Donnerstag, 14. Januar 2016, 20:34:20 schrieb Andy Yan:
> The current vdd_arm voltage is too low, increase it will make
> the system more stable.
> 
> Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> 
>  arch/arm/boot/dts/rk3066a-rayeager.dts | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts
> b/arch/arm/boot/dts/rk3066a-rayeager.dts index 0bf6876..3d4c104 100644
> --- a/arch/arm/boot/dts/rk3066a-rayeager.dts
> +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
> @@ -159,6 +159,14 @@
> 
>  &cpu0 {
>  	cpu0-supply = <&vdd_arm>;
> +	operating-points = <
> +		/* kHz    uV */
> +		1008000 1125000
> +		816000  1125000
> +		600000  1100000
> +		504000  1100000
> +		312000  1075000
> +	>;
>  };
> 
>  &emac {

Does this only apply to the rayeager-board / px2 soc or for all rk3066a/px2 
boards? I.e. the original values come from some sdk kernel and I might've 
transcribed that wrong at the time and I remember having problems trying to 
reach higher frequencies as well.

So could you check what the full operating points looks like for both and if 
this can move to the rk3066a.dtsi, as both should be able to reach at least 
1.4GHz / 1.6GHz.


Thanks
Heiko
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Re: [PATCH 1/2] ARM: dts: rockchip: increase vdd_arm voltage for rk3066a-rayeager board

[Andy Yan]

Hi Heiko:

On 2016年01月14日 20:45, Heiko Stuebner wrote:
> Hi Andy,
>
> Am Donnerstag, 14. Januar 2016, 20:34:20 schrieb Andy Yan:
>> The current vdd_arm voltage is too low, increase it will make
>> the system more stable.
>>
>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>> ---
>>
>>   arch/arm/boot/dts/rk3066a-rayeager.dts | 8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts
>> b/arch/arm/boot/dts/rk3066a-rayeager.dts index 0bf6876..3d4c104 100644
>> --- a/arch/arm/boot/dts/rk3066a-rayeager.dts
>> +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
>> @@ -159,6 +159,14 @@
>>
>>   &cpu0 {
>>   	cpu0-supply = <&vdd_arm>;
>> +	operating-points = <
>> +		/* kHz    uV */
>> +		1008000 1125000
>> +		816000  1125000
>> +		600000  1100000
>> +		504000  1100000
>> +		312000  1075000
>> +	>;
>>   };
>>
>>   &emac {
> Does this only apply to the rayeager-board / px2 soc or for all rk3066a/px2
> boards? I.e. the original values come from some sdk kernel and I might've
> transcribed that wrong at the time and I remember having problems trying to
> reach higher frequencies as well.
>
> So could you check what the full operating points looks like for both and if
> this can move to the rk3066a.dtsi, as both should be able to reach at least
> 1.4GHz / 1.6GHz.
>
>
> Thanks
> Heiko
>
> ______

     I have checked the sdk kernel, the opp for the sdk board is like 
bellow:

  /**
  * dvfs_cpu_logic_table: table for arm and logic dvfs
  * @frequency   : arm frequency
  * @cpu_volt    : arm voltage depend on frequency
  * @logic_volt  : logic voltage arm requests depend on frequency
  * comments     : min arm/logic voltage
  */
static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
         {.frequency = 252 * 1000,       .cpu_volt = 1075 * 1000,        
.logic_volt = 1125 * 1000},//0.975V/1.000V
         {.frequency = 504 * 1000,       .cpu_volt = 1100 * 1000,        
.logic_volt = 1125 * 1000},//0.975V/1.000V
         {.frequency = 816 * 1000,       .cpu_volt = 1125 * 1000,        
.logic_volt = 1150 * 1000},//1.000V/1.025V
         {.frequency = 1008 * 1000,      .cpu_volt = 1125 * 1000,        
.logic_volt = 1150 * 1000},//1.025V/1.050V
         {.frequency = 1200 * 1000,      .cpu_volt = 1175 * 1000,        
.logic_volt = 1200 * 1000},//1.100V/1.050V
         {.frequency = 1272 * 1000,      .cpu_volt = 1225 * 1000,        
.logic_volt = 1200 * 1000},//1.150V/1.100V
         {.frequency = 1416 * 1000,      .cpu_volt = 1300 * 1000,        
.logic_volt = 1200 * 1000},//1.225V/1.100V
         {.frequency = 1512 * 1000,      .cpu_volt = 1350 * 1000,        
.logic_volt = 1250 * 1000},//1.300V/1.150V
         {.frequency = 1608 * 1000,      .cpu_volt = 1425 * 1000,        
.logic_volt = 1300 * 1000},//1.325V/1.175V
         {.frequency = CPUFREQ_TABLE_END},
};

  This table is made base on mass stress test. So is a safe opp table 
for most rk3066a base boards. But it some
  board is not so well in power supply circuit design, the may also need 
to adjust it.

  From the table we see that the logic_voltage need to increase  as the 
cpufreq increase. But it seems that the current mainline kernel does not 
support adjust the logic voltage when cpufreq change. So we can only 
scale the cpufreq to 1.4GHZ by fixed the logic_volt at 1.2V.

  If you like, I can move it to rk3066a.dtsi with the max freq at 
1008MHZ, as I haven't  test to 1.4GHZ  with the mainline kernel. Or give 
me some time to test to see if the rayeager board can run to 1.4G stable 
with the mainline .
> _________________________________________
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> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
>
>
>




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Re: [PATCH 1/2] ARM: dts: rockchip: increase vdd_arm voltage for rk3066a-rayeager board

[Eddie Cai]

Hi Heiko

I don't want open source version kernel support too high frequency.
Many people use RK3066/PX2 on their board. We don't know if their
layout is good enough to support higher frequency. ie. bad layout will
cause more voltage drop on the VDD_CPU power rail. So it may need
higher voltage. I think stable is more important here. People want
higher frequency can add more opp depend on their board's layout.

2016-01-14 21:20 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
> Hi Heiko:
>
>
> On 2016年01月14日 20:45, Heiko Stuebner wrote:
>>
>> Hi Andy,
>>
>> Am Donnerstag, 14. Januar 2016, 20:34:20 schrieb Andy Yan:
>>>
>>> The current vdd_arm voltage is too low, increase it will make
>>> the system more stable.
>>>
>>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>>> ---
>>>
>>>   arch/arm/boot/dts/rk3066a-rayeager.dts | 8 ++++++++
>>>   1 file changed, 8 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts
>>> b/arch/arm/boot/dts/rk3066a-rayeager.dts index 0bf6876..3d4c104 100644
>>> --- a/arch/arm/boot/dts/rk3066a-rayeager.dts
>>> +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
>>> @@ -159,6 +159,14 @@
>>>
>>>   &cpu0 {
>>>         cpu0-supply = <&vdd_arm>;
>>> +       operating-points = <
>>> +               /* kHz    uV */
>>> +               1008000 1125000
>>> +               816000  1125000
>>> +               600000  1100000
>>> +               504000  1100000
>>> +               312000  1075000
>>> +       >;
>>>   };
>>>
>>>   &emac {
>>
>> Does this only apply to the rayeager-board / px2 soc or for all
>> rk3066a/px2
>> boards? I.e. the original values come from some sdk kernel and I might've
>> transcribed that wrong at the time and I remember having problems trying
>> to
>> reach higher frequencies as well.
>>
>> So could you check what the full operating points looks like for both and
>> if
>> this can move to the rk3066a.dtsi, as both should be able to reach at
>> least
>> 1.4GHz / 1.6GHz.
>>
>>
>> Thanks
>> Heiko
>>
>> ______
>
>
>     I have checked the sdk kernel, the opp for the sdk board is like bellow:
>
>  /**
>  * dvfs_cpu_logic_table: table for arm and logic dvfs
>  * @frequency   : arm frequency
>  * @cpu_volt    : arm voltage depend on frequency
>  * @logic_volt  : logic voltage arm requests depend on frequency
>  * comments     : min arm/logic voltage
>  */
> static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
>         {.frequency = 252 * 1000,       .cpu_volt = 1075 * 1000,
> .logic_volt = 1125 * 1000},//0.975V/1.000V
>         {.frequency = 504 * 1000,       .cpu_volt = 1100 * 1000,
> .logic_volt = 1125 * 1000},//0.975V/1.000V
>         {.frequency = 816 * 1000,       .cpu_volt = 1125 * 1000,
> .logic_volt = 1150 * 1000},//1.000V/1.025V
>         {.frequency = 1008 * 1000,      .cpu_volt = 1125 * 1000,
> .logic_volt = 1150 * 1000},//1.025V/1.050V
>         {.frequency = 1200 * 1000,      .cpu_volt = 1175 * 1000,
> .logic_volt = 1200 * 1000},//1.100V/1.050V
>         {.frequency = 1272 * 1000,      .cpu_volt = 1225 * 1000,
> .logic_volt = 1200 * 1000},//1.150V/1.100V
>         {.frequency = 1416 * 1000,      .cpu_volt = 1300 * 1000,
> .logic_volt = 1200 * 1000},//1.225V/1.100V
>         {.frequency = 1512 * 1000,      .cpu_volt = 1350 * 1000,
> .logic_volt = 1250 * 1000},//1.300V/1.150V
>         {.frequency = 1608 * 1000,      .cpu_volt = 1425 * 1000,
> .logic_volt = 1300 * 1000},//1.325V/1.175V
>         {.frequency = CPUFREQ_TABLE_END},
> };
>
>  This table is made base on mass stress test. So is a safe opp table for
> most rk3066a base boards. But it some
>  board is not so well in power supply circuit design, the may also need to
> adjust it.
>
>  From the table we see that the logic_voltage need to increase  as the
> cpufreq increase. But it seems that the current mainline kernel does not
> support adjust the logic voltage when cpufreq change. So we can only scale
> the cpufreq to 1.4GHZ by fixed the logic_volt at 1.2V.
>
>  If you like, I can move it to rk3066a.dtsi with the max freq at 1008MHZ, as
> I haven't  test to 1.4GHZ  with the mainline kernel. Or give me some time to
> test to see if the rayeager board can run to 1.4G stable with the mainline .
>
>> _________________________________________
>> Linux-rockchip mailing list
>> Linux-rockchip@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>>
>>
>>
>>
>
>
>
>
> _______________________________________________
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> http://lists.infradead.org/mailman/listinfo/linux-rockchip

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Re: [PATCH 1/2] ARM: dts: rockchip: increase vdd_arm voltage for rk3066a-rayeager board

[Andy Yan]

Hi Heiko:

On 2016年01月14日 21:50, Eddie Cai wrote:
> Hi Heiko
>
> I don't want open source version kernel support too high frequency.
> Many people use RK3066/PX2 on their board. We don't know if their
> layout is good enough to support higher frequency. ie. bad layout will
> cause more voltage drop on the VDD_CPU power rail. So it may need
> higher voltage. I think stable is more important here. People want
> higher frequency can add more opp depend on their board's layout.
>
> 2016-01-14 21:20 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
>> Hi Heiko:
>>
>>
>> On 2016年01月14日 20:45, Heiko Stuebner wrote:
>>> Hi Andy,
>>>
>>> Am Donnerstag, 14. Januar 2016, 20:34:20 schrieb Andy Yan:
>>>> The current vdd_arm voltage is too low, increase it will make
>>>> the system more stable.
>>>>
>>>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>>>> ---
>>>>
>>>>    arch/arm/boot/dts/rk3066a-rayeager.dts | 8 ++++++++
>>>>    1 file changed, 8 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts
>>>> b/arch/arm/boot/dts/rk3066a-rayeager.dts index 0bf6876..3d4c104 100644
>>>> --- a/arch/arm/boot/dts/rk3066a-rayeager.dts
>>>> +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
>>>> @@ -159,6 +159,14 @@
>>>>
>>>>    &cpu0 {
>>>>          cpu0-supply = <&vdd_arm>;
>>>> +       operating-points = <
>>>> +               /* kHz    uV */
>>>> +               1008000 1125000
>>>> +               816000  1125000
>>>> +               600000  1100000
>>>> +               504000  1100000
>>>> +               312000  1075000
>>>> +       >;
>>>>    };
>>>>
>>>>    &emac {
>>> Does this only apply to the rayeager-board / px2 soc or for all
>>> rk3066a/px2
>>> boards? I.e. the original values come from some sdk kernel and I might've
>>> transcribed that wrong at the time and I remember having problems trying
>>> to
>>> reach higher frequencies as well.
>>>
>>> So could you check what the full operating points looks like for both and
>>> if
>>> this can move to the rk3066a.dtsi, as both should be able to reach at
>>> least
>>> 1.4GHz / 1.6GHz.
>>>
>>>
>>> Thanks
>>> Heiko
>>>
>>> ______
>>
>>      I have checked the sdk kernel, the opp for the sdk board is like bellow:
>>
>>   /**
>>   * dvfs_cpu_logic_table: table for arm and logic dvfs
>>   * @frequency   : arm frequency
>>   * @cpu_volt    : arm voltage depend on frequency
>>   * @logic_volt  : logic voltage arm requests depend on frequency
>>   * comments     : min arm/logic voltage
>>   */
>> static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
>>          {.frequency = 252 * 1000,       .cpu_volt = 1075 * 1000,
>> .logic_volt = 1125 * 1000},//0.975V/1.000V
>>          {.frequency = 504 * 1000,       .cpu_volt = 1100 * 1000,
>> .logic_volt = 1125 * 1000},//0.975V/1.000V
>>          {.frequency = 816 * 1000,       .cpu_volt = 1125 * 1000,
>> .logic_volt = 1150 * 1000},//1.000V/1.025V
>>          {.frequency = 1008 * 1000,      .cpu_volt = 1125 * 1000,
>> .logic_volt = 1150 * 1000},//1.025V/1.050V
>>          {.frequency = 1200 * 1000,      .cpu_volt = 1175 * 1000,
>> .logic_volt = 1200 * 1000},//1.100V/1.050V
>>          {.frequency = 1272 * 1000,      .cpu_volt = 1225 * 1000,
>> .logic_volt = 1200 * 1000},//1.150V/1.100V
>>          {.frequency = 1416 * 1000,      .cpu_volt = 1300 * 1000,
>> .logic_volt = 1200 * 1000},//1.225V/1.100V
>>          {.frequency = 1512 * 1000,      .cpu_volt = 1350 * 1000,
>> .logic_volt = 1250 * 1000},//1.300V/1.150V
>>          {.frequency = 1608 * 1000,      .cpu_volt = 1425 * 1000,
>> .logic_volt = 1300 * 1000},//1.325V/1.175V
>>          {.frequency = CPUFREQ_TABLE_END},
>> };
>>
>>   This table is made base on mass stress test. So is a safe opp table for
>> most rk3066a base boards. But it some
>>   board is not so well in power supply circuit design, the may also need to
>> adjust it.
>>
>>   From the table we see that the logic_voltage need to increase  as the
>> cpufreq increase. But it seems that the current mainline kernel does not
>> support adjust the logic voltage when cpufreq change. So we can only scale
>> the cpufreq to 1.4GHZ by fixed the logic_volt at 1.2V.
>>
>>   If you like, I can move it to rk3066a.dtsi with the max freq at 1008MHZ, as
>> I haven't  test to 1.4GHZ  with the mainline kernel. Or give me some time to
>> test to see if the rayeager board can run to 1.4G stable with the mainline .
>>
>>

   I have run Rayeager  board with cpufreq freely change from 
312MHZ~1416MHZ for 11 hours now, it's stable. Maybe we can set the 
default opp table for rk3066a/PX2 from 312MHZ~1416HZ in current mainline.



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Re: [PATCH 1/2] ARM: dts: rockchip: increase vdd_arm voltage for rk3066a-rayeager board

[Heiko Stuebner]

Hi Andy, Eddie,

Am Freitag, 15. Januar 2016, 09:11:16 schrieb Andy Yan:
> On 2016年01月14日 21:50, Eddie Cai wrote:
> > Hi Heiko
> > 
> > I don't want open source version kernel support too high frequency.
> > Many people use RK3066/PX2 on their board. We don't know if their
> > layout is good enough to support higher frequency. ie. bad layout will
> > cause more voltage drop on the VDD_CPU power rail. So it may need
> > higher voltage. I think stable is more important here. People want
> > higher frequency can add more opp depend on their board's layout.
> > 
> > 2016-01-14 21:20 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
> >> Hi Heiko:
> >> 
> >> On 2016年01月14日 20:45, Heiko Stuebner wrote:
> >>> Hi Andy,
> >>> 
> >>> Am Donnerstag, 14. Januar 2016, 20:34:20 schrieb Andy Yan:
> >>>> The current vdd_arm voltage is too low, increase it will make
> >>>> the system more stable.
> >>>> 
> >>>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> >>>> ---
> >>>> 
> >>>>    arch/arm/boot/dts/rk3066a-rayeager.dts | 8 ++++++++
> >>>>    1 file changed, 8 insertions(+)
> >>>> 
> >>>> diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts
> >>>> b/arch/arm/boot/dts/rk3066a-rayeager.dts index 0bf6876..3d4c104
> >>>> 100644
> >>>> --- a/arch/arm/boot/dts/rk3066a-rayeager.dts
> >>>> +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
> >>>> @@ -159,6 +159,14 @@
> >>>> 
> >>>>    &cpu0 {
> >>>>    
> >>>>          cpu0-supply = <&vdd_arm>;
> >>>> 
> >>>> +       operating-points = <
> >>>> +               /* kHz    uV */
> >>>> +               1008000 1125000
> >>>> +               816000  1125000
> >>>> +               600000  1100000
> >>>> +               504000  1100000
> >>>> +               312000  1075000
> >>>> +       >;
> >>>> 
> >>>>    };
> >>>>    
> >>>>    &emac {
> >>> 
> >>> Does this only apply to the rayeager-board / px2 soc or for all
> >>> rk3066a/px2
> >>> boards? I.e. the original values come from some sdk kernel and I
> >>> might've
> >>> transcribed that wrong at the time and I remember having problems
> >>> trying
> >>> to
> >>> reach higher frequencies as well.
> >>> 
> >>> So could you check what the full operating points looks like for both
> >>> and
> >>> if
> >>> this can move to the rk3066a.dtsi, as both should be able to reach at
> >>> least
> >>> 1.4GHz / 1.6GHz.
> >>> 
> >>> 
> >>> Thanks
> >>> Heiko
> >>> 
> >>> ______
> >>> 
> >>      I have checked the sdk kernel, the opp for the sdk board is like 
bellow:
> >>   /**
> >>   * dvfs_cpu_logic_table: table for arm and logic dvfs
> >>   * @frequency   : arm frequency
> >>   * @cpu_volt    : arm voltage depend on frequency
> >>   * @logic_volt  : logic voltage arm requests depend on frequency
> >>   * comments     : min arm/logic voltage
> >>   */
> >> 
> >> static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
> >> 
> >>          {.frequency = 252 * 1000,       .cpu_volt = 1075 * 1000,
> >> 
> >> .logic_volt = 1125 * 1000},//0.975V/1.000V
> >> 
> >>          {.frequency = 504 * 1000,       .cpu_volt = 1100 * 1000,
> >> 
> >> .logic_volt = 1125 * 1000},//0.975V/1.000V
> >> 
> >>          {.frequency = 816 * 1000,       .cpu_volt = 1125 * 1000,
> >> 
> >> .logic_volt = 1150 * 1000},//1.000V/1.025V
> >> 
> >>          {.frequency = 1008 * 1000,      .cpu_volt = 1125 * 1000,
> >> 
> >> .logic_volt = 1150 * 1000},//1.025V/1.050V
> >> 
> >>          {.frequency = 1200 * 1000,      .cpu_volt = 1175 * 1000,
> >> 
> >> .logic_volt = 1200 * 1000},//1.100V/1.050V
> >> 
> >>          {.frequency = 1272 * 1000,      .cpu_volt = 1225 * 1000,
> >> 
> >> .logic_volt = 1200 * 1000},//1.150V/1.100V
> >> 
> >>          {.frequency = 1416 * 1000,      .cpu_volt = 1300 * 1000,
> >> 
> >> .logic_volt = 1200 * 1000},//1.225V/1.100V
> >> 
> >>          {.frequency = 1512 * 1000,      .cpu_volt = 1350 * 1000,
> >> 
> >> .logic_volt = 1250 * 1000},//1.300V/1.150V
> >> 
> >>          {.frequency = 1608 * 1000,      .cpu_volt = 1425 * 1000,
> >> 
> >> .logic_volt = 1300 * 1000},//1.325V/1.175V
> >> 
> >>          {.frequency = CPUFREQ_TABLE_END},
> >> 
> >> };
> >> 
> >>   This table is made base on mass stress test. So is a safe opp table
> >>   for
> >> 
> >> most rk3066a base boards. But it some
> >> 
> >>   board is not so well in power supply circuit design, the may also
> >>   need to
> >> 
> >> adjust it.
> >> 
> >>   From the table we see that the logic_voltage need to increase  as the
> >> 
> >> cpufreq increase. But it seems that the current mainline kernel does
> >> not
> >> support adjust the logic voltage when cpufreq change. So we can only
> >> scale the cpufreq to 1.4GHZ by fixed the logic_volt at 1.2V.
> >> 
> >>   If you like, I can move it to rk3066a.dtsi with the max freq at
> >>   1008MHZ, as>> 
> >> I haven't  test to 1.4GHZ  with the mainline kernel. Or give me some
> >> time to test to see if the rayeager board can run to 1.4G stable with
> >> the mainline .
>    I have run Rayeager  board with cpufreq freely change from
> 312MHZ~1416MHZ for 11 hours now, it's stable. Maybe we can set the
> default opp table for rk3066a/PX2 from 312MHZ~1416HZ in current mainline.

Thanks for doing that stress test and making that the default setting would 
be a nice way to go :-) .

I just checked, the other 2 rk3066a boards we currently support (Hayou 
Marsboard and BQ Curie2) use the exact same power-layout (tps65210 + pwm-
regulator for vdd_log), so should be quite save to do.


Heiko
Heiko

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Re: [PATCH 1/2] ARM: dts: rockchip: increase vdd_arm voltage for rk3066a-rayeager board

[Andy Yan]

Hi Heiko:

On 2016年01月15日 17:22, Heiko Stuebner wrote:
> Hi Andy, Eddie,
>
> Am Freitag, 15. Januar 2016, 09:11:16 schrieb Andy Yan:
>> On 2016年01月14日 21:50, Eddie Cai wrote:
>>> Hi Heiko
>>>
>>> I don't want open source version kernel support too high frequency.
>>> Many people use RK3066/PX2 on their board. We don't know if their
>>> layout is good enough to support higher frequency. ie. bad layout will
>>> cause more voltage drop on the VDD_CPU power rail. So it may need
>>> higher voltage. I think stable is more important here. People want
>>> higher frequency can add more opp depend on their board's layout.
>>>
>>> 2016-01-14 21:20 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
>>>> Hi Heiko:
>>>>
>>>> On 2016年01月14日 20:45, Heiko Stuebner wrote:
>>>>> Hi Andy,
>>>>>
>>>>> Am Donnerstag, 14. Januar 2016, 20:34:20 schrieb Andy Yan:
>>>>>> The current vdd_arm voltage is too low, increase it will make
>>>>>> the system more stable.
>>>>>>
>>>>>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>>>>>> ---
>>>>>>
>>>>>>     arch/arm/boot/dts/rk3066a-rayeager.dts | 8 ++++++++
>>>>>>     1 file changed, 8 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts
>>>>>> b/arch/arm/boot/dts/rk3066a-rayeager.dts index 0bf6876..3d4c104
>>>>>> 100644
>>>>>> --- a/arch/arm/boot/dts/rk3066a-rayeager.dts
>>>>>> +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
>>>>>> @@ -159,6 +159,14 @@
>>>>>>
>>>>>>     &cpu0 {
>>>>>>     
>>>>>>           cpu0-supply = <&vdd_arm>;
>>>>>>
>>>>>> +       operating-points = <
>>>>>> +               /* kHz    uV */
>>>>>> +               1008000 1125000
>>>>>> +               816000  1125000
>>>>>> +               600000  1100000
>>>>>> +               504000  1100000
>>>>>> +               312000  1075000
>>>>>> +       >;
>>>>>>
>>>>>>     };
>>>>>>     
>>>>>>     &emac {
>>>>> Does this only apply to the rayeager-board / px2 soc or for all
>>>>> rk3066a/px2
>>>>> boards? I.e. the original values come from some sdk kernel and I
>>>>> might've
>>>>> transcribed that wrong at the time and I remember having problems
>>>>> trying
>>>>> to
>>>>> reach higher frequencies as well.
>>>>>
>>>>> So could you check what the full operating points looks like for both
>>>>> and
>>>>> if
>>>>> this can move to the rk3066a.dtsi, as both should be able to reach at
>>>>> least
>>>>> 1.4GHz / 1.6GHz.
>>>>>
>>>>>
>>>>> Thanks
>>>>> Heiko
>>>>>
>>>>> ______
>>>>>
>>>>       I have checked the sdk kernel, the opp for the sdk board is like
> bellow:
>>>>    /**
>>>>    * dvfs_cpu_logic_table: table for arm and logic dvfs
>>>>    * @frequency   : arm frequency
>>>>    * @cpu_volt    : arm voltage depend on frequency
>>>>    * @logic_volt  : logic voltage arm requests depend on frequency
>>>>    * comments     : min arm/logic voltage
>>>>    */
>>>>
>>>> static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
>>>>
>>>>           {.frequency = 252 * 1000,       .cpu_volt = 1075 * 1000,
>>>>
>>>> .logic_volt = 1125 * 1000},//0.975V/1.000V
>>>>
>>>>           {.frequency = 504 * 1000,       .cpu_volt = 1100 * 1000,
>>>>
>>>> .logic_volt = 1125 * 1000},//0.975V/1.000V
>>>>
>>>>           {.frequency = 816 * 1000,       .cpu_volt = 1125 * 1000,
>>>>
>>>> .logic_volt = 1150 * 1000},//1.000V/1.025V
>>>>
>>>>           {.frequency = 1008 * 1000,      .cpu_volt = 1125 * 1000,
>>>>
>>>> .logic_volt = 1150 * 1000},//1.025V/1.050V
>>>>
>>>>           {.frequency = 1200 * 1000,      .cpu_volt = 1175 * 1000,
>>>>
>>>> .logic_volt = 1200 * 1000},//1.100V/1.050V
>>>>
>>>>           {.frequency = 1272 * 1000,      .cpu_volt = 1225 * 1000,
>>>>
>>>> .logic_volt = 1200 * 1000},//1.150V/1.100V
>>>>
>>>>           {.frequency = 1416 * 1000,      .cpu_volt = 1300 * 1000,
>>>>
>>>> .logic_volt = 1200 * 1000},//1.225V/1.100V
>>>>
>>>>           {.frequency = 1512 * 1000,      .cpu_volt = 1350 * 1000,
>>>>
>>>> .logic_volt = 1250 * 1000},//1.300V/1.150V
>>>>
>>>>           {.frequency = 1608 * 1000,      .cpu_volt = 1425 * 1000,
>>>>
>>>> .logic_volt = 1300 * 1000},//1.325V/1.175V
>>>>
>>>>           {.frequency = CPUFREQ_TABLE_END},
>>>>
>>>> };
>>>>
>>>>    This table is made base on mass stress test. So is a safe opp table
>>>>    for
>>>>
>>>> most rk3066a base boards. But it some
>>>>
>>>>    board is not so well in power supply circuit design, the may also
>>>>    need to
>>>>
>>>> adjust it.
>>>>
>>>>    From the table we see that the logic_voltage need to increase  as the
>>>>
>>>> cpufreq increase. But it seems that the current mainline kernel does
>>>> not
>>>> support adjust the logic voltage when cpufreq change. So we can only
>>>> scale the cpufreq to 1.4GHZ by fixed the logic_volt at 1.2V.
>>>>
>>>>    If you like, I can move it to rk3066a.dtsi with the max freq at
>>>>    1008MHZ, as>>
>>>> I haven't  test to 1.4GHZ  with the mainline kernel. Or give me some
>>>> time to test to see if the rayeager board can run to 1.4G stable with
>>>> the mainline .
>>     I have run Rayeager  board with cpufreq freely change from
>> 312MHZ~1416MHZ for 11 hours now, it's stable. Maybe we can set the
>> default opp table for rk3066a/PX2 from 312MHZ~1416HZ in current mainline.
> Thanks for doing that stress test and making that the default setting would
> be a nice way to go :-) .
>
> I just checked, the other 2 rk3066a boards we currently support (Hayou
> Marsboard and BQ Curie2) use the exact same power-layout (tps65210 + pwm-
> regulator for vdd_log), so should be quite save to do.
>
>
> Heiko
> Heiko
>
>
>
>
   Actually, all the rockchip rk3066 base platform use the same power 
supply design( control vdd_logic voltage by pwm).
   So I can move the opp table with max freq 1416MHZ to rk3066a.dtsi and 
keep the pwm-regulator in board specific dts?



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Re: [PATCH 1/2] ARM: dts: rockchip: increase vdd_arm voltage for rk3066a-rayeager board

[Heiko Stuebner]

Am Freitag, 15. Januar 2016, 17:34:31 schrieb Andy Yan:
> Hi Heiko:
> 
> On 2016年01月15日 17:22, Heiko Stuebner wrote:
> > Hi Andy, Eddie,
> > 
> > Am Freitag, 15. Januar 2016, 09:11:16 schrieb Andy Yan:
> >> On 2016年01月14日 21:50, Eddie Cai wrote:
> >>> Hi Heiko
> >>> 
> >>> I don't want open source version kernel support too high frequency.
> >>> Many people use RK3066/PX2 on their board. We don't know if their
> >>> layout is good enough to support higher frequency. ie. bad layout will
> >>> cause more voltage drop on the VDD_CPU power rail. So it may need
> >>> higher voltage. I think stable is more important here. People want
> >>> higher frequency can add more opp depend on their board's layout.
> >>> 
> >>> 2016-01-14 21:20 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
> >>>> Hi Heiko:
> >>>> 
> >>>> On 2016年01月14日 20:45, Heiko Stuebner wrote:
> >>>>> Hi Andy,
> >>>>> 
> >>>>> Am Donnerstag, 14. Januar 2016, 20:34:20 schrieb Andy Yan:
> >>>>>> The current vdd_arm voltage is too low, increase it will make
> >>>>>> the system more stable.
> >>>>>> 
> >>>>>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> >>>>>> ---
> >>>>>> 
> >>>>>>     arch/arm/boot/dts/rk3066a-rayeager.dts | 8 ++++++++
> >>>>>>     1 file changed, 8 insertions(+)
> >>>>>> 
> >>>>>> diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts
> >>>>>> b/arch/arm/boot/dts/rk3066a-rayeager.dts index 0bf6876..3d4c104
> >>>>>> 100644
> >>>>>> --- a/arch/arm/boot/dts/rk3066a-rayeager.dts
> >>>>>> +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
> >>>>>> @@ -159,6 +159,14 @@
> >>>>>> 
> >>>>>>     &cpu0 {
> >>>>>>     
> >>>>>>           cpu0-supply = <&vdd_arm>;
> >>>>>> 
> >>>>>> +       operating-points = <
> >>>>>> +               /* kHz    uV */
> >>>>>> +               1008000 1125000
> >>>>>> +               816000  1125000
> >>>>>> +               600000  1100000
> >>>>>> +               504000  1100000
> >>>>>> +               312000  1075000
> >>>>>> +       >;
> >>>>>> 
> >>>>>>     };
> >>>>>>     
> >>>>>>     &emac {
> >>>>> 
> >>>>> Does this only apply to the rayeager-board / px2 soc or for all
> >>>>> rk3066a/px2
> >>>>> boards? I.e. the original values come from some sdk kernel and I
> >>>>> might've
> >>>>> transcribed that wrong at the time and I remember having problems
> >>>>> trying
> >>>>> to
> >>>>> reach higher frequencies as well.
> >>>>> 
> >>>>> So could you check what the full operating points looks like for
> >>>>> both
> >>>>> and
> >>>>> if
> >>>>> this can move to the rk3066a.dtsi, as both should be able to reach
> >>>>> at
> >>>>> least
> >>>>> 1.4GHz / 1.6GHz.
> >>>>> 
> >>>>> 
> >>>>> Thanks
> >>>>> Heiko
> >>>>> 
> >>>>> ______
> >>>>> 
> >>>>       I have checked the sdk kernel, the opp for the sdk board is
> >>>>       like
> > 
> > bellow:
> >>>>    /**
> >>>>    * dvfs_cpu_logic_table: table for arm and logic dvfs
> >>>>    * @frequency   : arm frequency
> >>>>    * @cpu_volt    : arm voltage depend on frequency
> >>>>    * @logic_volt  : logic voltage arm requests depend on frequency
> >>>>    * comments     : min arm/logic voltage
> >>>>    */
> >>>> 
> >>>> static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
> >>>> 
> >>>>           {.frequency = 252 * 1000,       .cpu_volt = 1075 * 1000,
> >>>> 
> >>>> .logic_volt = 1125 * 1000},//0.975V/1.000V
> >>>> 
> >>>>           {.frequency = 504 * 1000,       .cpu_volt = 1100 * 1000,
> >>>> 
> >>>> .logic_volt = 1125 * 1000},//0.975V/1.000V
> >>>> 
> >>>>           {.frequency = 816 * 1000,       .cpu_volt = 1125 * 1000,
> >>>> 
> >>>> .logic_volt = 1150 * 1000},//1.000V/1.025V
> >>>> 
> >>>>           {.frequency = 1008 * 1000,      .cpu_volt = 1125 * 1000,
> >>>> 
> >>>> .logic_volt = 1150 * 1000},//1.025V/1.050V
> >>>> 
> >>>>           {.frequency = 1200 * 1000,      .cpu_volt = 1175 * 1000,
> >>>> 
> >>>> .logic_volt = 1200 * 1000},//1.100V/1.050V
> >>>> 
> >>>>           {.frequency = 1272 * 1000,      .cpu_volt = 1225 * 1000,
> >>>> 
> >>>> .logic_volt = 1200 * 1000},//1.150V/1.100V
> >>>> 
> >>>>           {.frequency = 1416 * 1000,      .cpu_volt = 1300 * 1000,
> >>>> 
> >>>> .logic_volt = 1200 * 1000},//1.225V/1.100V
> >>>> 
> >>>>           {.frequency = 1512 * 1000,      .cpu_volt = 1350 * 1000,
> >>>> 
> >>>> .logic_volt = 1250 * 1000},//1.300V/1.150V
> >>>> 
> >>>>           {.frequency = 1608 * 1000,      .cpu_volt = 1425 * 1000,
> >>>> 
> >>>> .logic_volt = 1300 * 1000},//1.325V/1.175V
> >>>> 
> >>>>           {.frequency = CPUFREQ_TABLE_END},
> >>>> 
> >>>> };
> >>>> 
> >>>>    This table is made base on mass stress test. So is a safe opp
> >>>>    table
> >>>>    for
> >>>> 
> >>>> most rk3066a base boards. But it some
> >>>> 
> >>>>    board is not so well in power supply circuit design, the may also
> >>>>    need to
> >>>> 
> >>>> adjust it.
> >>>> 
> >>>>    From the table we see that the logic_voltage need to increase  as
> >>>>    the
> >>>> 
> >>>> cpufreq increase. But it seems that the current mainline kernel does
> >>>> not
> >>>> support adjust the logic voltage when cpufreq change. So we can only
> >>>> scale the cpufreq to 1.4GHZ by fixed the logic_volt at 1.2V.
> >>>> 
> >>>>    If you like, I can move it to rk3066a.dtsi with the max freq at
> >>>>    1008MHZ, as>>
> >>>> 
> >>>> I haven't  test to 1.4GHZ  with the mainline kernel. Or give me some
> >>>> time to test to see if the rayeager board can run to 1.4G stable with
> >>>> the mainline .
> >>>> 
> >>     I have run Rayeager  board with cpufreq freely change from
> >> 
> >> 312MHZ~1416MHZ for 11 hours now, it's stable. Maybe we can set the
> >> default opp table for rk3066a/PX2 from 312MHZ~1416HZ in current
> >> mainline.
> > 
> > Thanks for doing that stress test and making that the default setting
> > would be a nice way to go :-) .
> > 
> > I just checked, the other 2 rk3066a boards we currently support (Hayou
> > Marsboard and BQ Curie2) use the exact same power-layout (tps65210 +
> > pwm-
> > regulator for vdd_log), so should be quite save to do.
> > 
> > 
> > Heiko
> > Heiko
> 
>    Actually, all the rockchip rk3066 base platform use the same power
> supply design( control vdd_logic voltage by pwm).
>    So I can move the opp table with max freq 1416MHZ to rk3066a.dtsi and
> keep the pwm-regulator in board specific dts?

Yep, opp in dtsi and pwm-regulator in board files is the correct split.

I.e. that the pwm3 is hooked up to vdd_log is still a board-specific setup as 
there is a tiny chance that some (or future) board might diverge from that.
For the same reason we're having the nearly same setup for the act8846 in 
most board files and not in the core dtsi.


Heiko

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Re: [PATCH 2/2] ARM: dts: rockchip: enable pwm3 as pwm regulator for rk3066a-rayeager board

[Andy Yan]

Hi Heiko:

On 2016年01月14日 20:41, Heiko Stuebner wrote:
> Hi Andy,
>
> Am Donnerstag, 14. Januar 2016, 20:35:56 schrieb Andy Yan:
>> Rayeager board use pwm3 modulate the vdd_logic voltage, so enable it.
>>
>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>> ---
>>
>>   arch/arm/boot/dts/rk3066a-rayeager.dts | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts
>> b/arch/arm/boot/dts/rk3066a-rayeager.dts index 3d4c104..d17a5b8 100644
>> --- a/arch/arm/boot/dts/rk3066a-rayeager.dts
>> +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
>> @@ -78,6 +78,18 @@
>>   		};
>>   	};
>>
>> +	pwm_regulator: pwm-regulator {
>> +		compatible = "pwm-regulator";
>> +		pwms = <&pwm3 0 1000>;
>> +		regulator-name = "vdd_logic";
>> +		regulator-min-microvolt = <1200000>;
>> +		regulator-max-microvolt = <1200000>;
> I guess this is to make sure it stays at 1.2V at all times, or is the min-
> microvolt settings supposed to be lower?
>
>
> Thanks
> Heiko
>
>
>
    Yes, I want to fix it at 1.2V. When I read the regulator_register 
function,  I found it call regulator_do_set_voltate only when min=max. 
So I set it like what you see.
    regulator_register--->
                    set_machine_constrains--->
                                    machine_constrains_voltage-->




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