From mboxrd@z Thu Jan 1 00:00:00 1970 From: Elaine Zhang Subject: Re: [PATCH v1 2/2] rockchip: power-domain: support qos save and restore Date: Tue, 05 Apr 2016 09:57:20 +0800 Message-ID: <57031B80.1080602@rock-chips.com> References: <1458285444-31129-1-git-send-email-zhangqing@rock-chips.com> <6919893.LfaTZNRxZs@phil> <56FDDE09.9080601@rock-chips.com> <3121335.t9IV1BMS6Y@phil> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252"; Format="flowed" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <3121335.t9IV1BMS6Y@phil> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Heiko Stuebner Cc: huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org, xf-TNX95d0MmH7DzftRWevZcw@public.gmane.org, khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, xxx-TNX95d0MmH7DzftRWevZcw@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org, jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org List-Id: linux-rockchip.vger.kernel.org hi, Heiko: Thanks for your replay. For your questions, I also have the same concerns. On 04/02/2016 12:19 AM, Heiko Stuebner wrote: > Hi Elaine, > > Am Freitag, 1. April 2016, 10:33:45 schrieb Elaine Zhang: >> I agree with most of your modifications. >> Except, the u32 *qos_save_regs below > > you're right. I didn't take that into account when my open-coding my idea. > A bit more below: > >> On 04/01/2016 12:31 AM, Heiko Stuebner wrote: >>> Hi Elaine, >>> >>> Am Freitag, 18. M=E4rz 2016, 15:17:24 schrieb Elaine Zhang: >>>> support qos save and restore when power domain on/off. >>>> >>>> Signed-off-by: Elaine Zhang >>> >>> overall looks nice already ... some implementation-specific comments >>> below.> >>>> --- >>>> >>>> drivers/soc/rockchip/pm_domains.c | 87 >>>> >>>> +++++++++++++++++++++++++++++++++++++-- 1 file changed, 84 >>>> insertions(+), >>>> 3 deletions(-) >>>> >>>> diff --git a/drivers/soc/rockchip/pm_domains.c >>>> b/drivers/soc/rockchip/pm_domains.c index 18aee6b..c5f4be6 100644 >>>> --- a/drivers/soc/rockchip/pm_domains.c >>>> +++ b/drivers/soc/rockchip/pm_domains.c >>>> @@ -45,10 +45,21 @@ struct rockchip_pmu_info { >>>> >>>> const struct rockchip_domain_info *domain_info; >>>> >>>> }; >>>> >>>> +#define MAX_QOS_NODE_NUM 20 >>>> +#define MAX_QOS_REGS_NUM 5 >>>> +#define QOS_PRIORITY 0x08 >>>> +#define QOS_MODE 0x0c >>>> +#define QOS_BANDWIDTH 0x10 >>>> +#define QOS_SATURATION 0x14 >>>> +#define QOS_EXTCONTROL 0x18 >>>> + >>>> >>>> struct rockchip_pm_domain { >>>> >>>> struct generic_pm_domain genpd; >>>> const struct rockchip_domain_info *info; >>>> struct rockchip_pmu *pmu; >>>> >>>> + int num_qos; >>>> + struct regmap *qos_regmap[MAX_QOS_NODE_NUM]; >>>> + u32 qos_save_regs[MAX_QOS_NODE_NUM][MAX_QOS_REGS_NUM]; >>> >>> struct regmap **qos_regmap; >>> u32 *qos_save_regs; >> >> when we save and restore qos registers we need save five regs for every >> qos. like this : >> for (i =3D 0; i < pd->num_qos; i++) { >> regmap_read(pd->qos_regmap[i], >> QOS_PRIORITY, >> &pd->qos_save_regs[i][0]); >> regmap_read(pd->qos_regmap[i], >> QOS_MODE, >> &pd->qos_save_regs[i][1]); >> regmap_read(pd->qos_regmap[i], >> QOS_BANDWIDTH, >> &pd->qos_save_regs[i][2]); >> regmap_read(pd->qos_regmap[i], >> QOS_SATURATION, >> &pd->qos_save_regs[i][3]); >> regmap_read(pd->qos_regmap[i], >> QOS_EXTCONTROL, >> &pd->qos_save_regs[i][4]); >> } >> so we can not define qos_save_regs like u32 *qos_save_regs;, >> and apply buff like >> pd->qos_save_regs =3D kcalloc(pd->num_qos * MAX_QOS_REGS_NUM, sizeof(u32= ), >> GFP_KERNEL); > > so how about simply swapping indices and doing it like > > u32 *qos_save_regs[MAX_QOS_REGS_NUM]; > > for (i =3D 0; i < MAX_QOS_REGS_NUM; i++) { > qos_save_regs[i] =3D kcalloc(pd->num_qos, sizeof(u32)); > /* error handling here */ > } > > ... > regmap_read(pd->qos_regmap[i], > QOS_SATURATION, > &pd->qos_save_regs[3][i]); > ... I agree with you on this modification. > > > Asked the other way around, how did you measure to set MAX_QOS_REGS_NUM to > 20? From looking at the rk3399 TRM, it seems there are only 38 QoS > generators on the SoC in general (24 on the rk3288 with PD_VIO having a > maximum of 9 qos generators), so preparing for 20 seems a bit overkill ;-) > About the MAX_QOS_NODE_NUM I also have some uncertaibty. Although there are only 38 QoS on the RK3399(24 on the rk3288),but not = all of the pd need to power on/off.So not all QOS need save and restore. So about the MAX_QOS_NODE_NUM, what do you suggest. MAX_QOS_REGS_NUM is 5 because the QOS register is just 5 need save and = restore. like : #define QOS_PRIORITY 0x08 #define QOS_MODE 0x0c #define QOS_BANDWIDTH 0x10 #define QOS_SATURATION 0x14 #define QOS_EXTCONTROL 0x18 > > Heiko > > >