From mboxrd@z Thu Jan 1 00:00:00 1970 From: hl Subject: Re: [RFC PATCH v1 3/6] clk: rockchip: rk3399: add ddrc clock support Date: Mon, 6 Jun 2016 11:25:27 +0800 Message-ID: <5754ED27.1070402@rock-chips.com> References: <1464947719-6245-1-git-send-email-hl@rock-chips.com> <1464947719-6245-4-git-send-email-hl@rock-chips.com> <13084747.Amq298iRsd@diego> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <13084747.Amq298iRsd@diego> Sender: linux-clk-owner@vger.kernel.org To: =?UTF-8?Q?Heiko_St=c3=bcbner?= Cc: mark.yao@rock-chips.com, myungjoo.ham@samsung.com, mturquette@baylibre.com, sboyd@codeaurora.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, airlied@linux.ie, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, kyungmin.park@samsung.com, dianders@chromium.org, dbasehore@chromium.org, huangtao@rock-chips.com, typ@rock-chips.com List-Id: linux-rockchip.vger.kernel.org Hi Heiko, On 2016=E5=B9=B406=E6=9C=8803=E6=97=A5 20:56, Heiko St=C3=BCbner wrote: > Am Freitag, 3. Juni 2016, 17:55:16 schrieb Lin Huang: >> add ddrc clock setting, so we can do ddr frequency >> scaling on rk3399 platform in future. >> >> Signed-off-by: Lin Huang >> --- >> Changes in v1: >> - remove ddrc source CLK_IGNORE_UNUSED flag, Suggestion by Doug >> - move clk_ddrc and clk_ddrc_dpll_src to critical, Suggestion by Dou= g >> >> drivers/clk/rockchip/clk-rk3399.c | 20 ++++++++++++++++++++ >> 1 file changed, 20 insertions(+) >> >> diff --git a/drivers/clk/rockchip/clk-rk3399.c >> b/drivers/clk/rockchip/clk-rk3399.c index f1d8e44..29afb88 100644 >> --- a/drivers/clk/rockchip/clk-rk3399.c >> +++ b/drivers/clk/rockchip/clk-rk3399.c > [...] > >> @@ -1377,6 +1381,18 @@ static struct rockchip_clk_branch >> rk3399_clk_branches[] __initdata =3D { COMPOSITE_NOMUX(0, "clk_test"= , >> "clk_test_pre", CLK_IGNORE_UNUSED, RK3368_CLKSEL_CON(58), 0, 5, DFLA= GS, >> RK3368_CLKGATE_CON(13), 11, GFLAGS), >> + >> + /* ddrc */ >> + GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3), >> + 0, GFLAGS), >> + GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3), >> + 1, GFLAGS), >> + GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3), >> + 2, GFLAGS), >> + GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3), >> + 3, GFLAGS), >> + COMPOSITE_DDRC(SCLK_DDRCLK, "clk_ddrc", mux_ddrclk_p, 0, >> + RK3399_CLKSEL_CON(6), 4, 2, MFLAGS, 0, 3, DFLAGS), >> }; > as said in the other patch, just make this a regular COMPOSITE_NOGATE= with > CLK_DIVIDER_READ_ONLY | CLK_MUX_READ_ONLY until that interface to the= ATF > exists and is approved. > > That way you can still read back the clock rate without anything chan= ging the > clock-rate, but we don't need to add duplicate code for it. > > >> static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __init= data =3D { >> @@ -1487,6 +1503,10 @@ static const char *const rk3399_cru_critical_= clocks[] >> __initconst =3D { "gpll_hclk_perilp1_src", >> "gpll_aclk_perilp0_src", >> "gpll_aclk_perihp_src", >> + >> + /* ddrc */ >> + "clk_ddrc_dpll_src", > Why does your clk_ddrc_dpll_src need a separate critical entry. Any c= ode > changing the clk_ddrc parent should make sure the new parent is enabl= ed. (The > clock-framework of course does this already). Okay, thank you. > >> + "clk_ddrc", >> }; >> >> static const char *const rk3399_pmucru_critical_clocks[] __initcon= st =3D { > > Heiko > > > > --=20 Lin Huang