From: Yannick FERTRE <yannick.fertre-qxv4g6HH51o@public.gmane.org>
To: Adrian Ratiu
<adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>,
"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
Laurent Pinchart
<Laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Cc: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>,
Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>,
Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Jonas Karlman <jonas-uIzNG4q0ceqzQB+pC5nmwQ@public.gmane.org>,
Philippe CORNU <philippe.cornu-qxv4g6HH51o@public.gmane.org>,
"dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org"
<dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
"linux-imx-3arQi8VN3Tc@public.gmane.org"
<linux-imx-3arQi8VN3Tc@public.gmane.org>,
"kernel-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org"
<kernel-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>,
"linux-stm32-XDFAJ8BFU24N7RejjzZ/Li2xQDfSxrLKVpNB7YpNyf8@public.gmane.org"
<linux-stm32-XDFAJ8BFU24N7RejjzZ/Li2xQDfSxrLKVpNB7YpNyf8@public.gmane.org>,
Arnaud Ferraris
<arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Subject: Re: [PATCH v9 10/11] drm: bridge: dw-mipi-dsi: fix bad register field offsets
Date: Wed, 10 Jun 2020 12:22:07 +0000 [thread overview]
Message-ID: <673a3961-d5ef-b7cd-4301-43c1c2786ed1@st.com> (raw)
In-Reply-To: <20200609174959.955926-11-adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Hi Adrian,
thanks for the pach: tested on stm32mp1.
Tested-by: Yannick Fertré <yannick.fertre@st.com>
On 6/9/20 7:49 PM, Adrian Ratiu wrote:
> According to the DSI Host Registers sections available in the IMX,
> STM and RK ref manuals for 1.01, 1.30 and 1.31, the register fields
> are smaller or bigger than what's coded in the driver, leading to
> r/w in reserved spaces which might cause undefined behaviours.
>
> Tested-by: Adrian Pop <pop.adrian61@gmail.com>
> Tested-by: Arnaud Ferraris <arnaud.ferraris@collabora.com>
> Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.com>
> ---
> New in v6.
> ---
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 46 +++++++++----------
> 1 file changed, 23 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 1e47d40b5becb..d274216c5a7c2 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -316,7 +316,7 @@ struct dw_mipi_dsi_variant {
> static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
> .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
> .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
> - .cfg_dpi_vid = REG_FIELD(DSI_DPI_VCID, 0, 2),
> + .cfg_dpi_vid = REG_FIELD(DSI_DPI_VCID, 0, 1),
> .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
> .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
> .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
> @@ -325,29 +325,29 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
> .cfg_cmd_mode_dcs_sw_sr_en = REG_FIELD(DSI_CMD_MODE_CFG, 16, 18),
> .cfg_cmd_mode_dcs_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 19, 19),
> .cfg_cmd_mode_max_rd_pkt_size = REG_FIELD(DSI_CMD_MODE_CFG, 24, 24),
> - .cfg_cmd_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31),
> - .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
> - .cfg_vid_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31),
> + .cfg_cmd_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 0),
> + .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS, 0, 6),
> + .cfg_vid_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 0),
> .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
> .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
> .cfg_vid_mode_vpg_en = REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
> .cfg_vid_mode_vpg_horiz = REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
> - .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
> - .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
> - .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
> - .cfg_vid_hline_time = REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
> - .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
> - .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
> - .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
> - .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
> + .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 13),
> + .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 11),
> + .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 11),
> + .cfg_vid_hline_time = REG_FIELD(DSI_VID_HLINE_TIME, 0, 14),
> + .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 9),
> + .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 9),
> + .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 9),
> + .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 13),
> .cfg_phy_txrequestclkhs = REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
> - .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
> - .cfg_phy_max_rd_time = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
> + .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 15),
> + .cfg_phy_max_rd_time = REG_FIELD(DSI_PHY_TMR_CFG, 0, 14),
> .cfg_phy_lp2hs_time = REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
> .cfg_phy_hs2lp_time = REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
> - .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
> - .cfg_phy_lp2hs_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
> - .cfg_phy_hs2lp_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
> + .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 14),
> + .cfg_phy_lp2hs_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 0, 9),
> + .cfg_phy_hs2lp_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 16, 25),
> .cfg_phy_clklp2hs_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
> .cfg_phy_clkhs2lp_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 31),
> .cfg_phy_testclr = REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0),
> @@ -361,11 +361,11 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
> .cfg_pckhdl_cfg = REG_FIELD(DSI_PCKHDL_CFG, 0, 4),
> .cfg_hstx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 16, 31),
> .cfg_lprx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 0, 15),
> - .cfg_int_stat0 = REG_FIELD(DSI_INT_ST0, 0, 31),
> - .cfg_int_stat1 = REG_FIELD(DSI_INT_ST1, 0, 31),
> - .cfg_int_mask0 = REG_FIELD(DSI_INT_MSK0, 0, 31),
> - .cfg_int_mask1 = REG_FIELD(DSI_INT_MSK1, 0, 31),
> - .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR, 0, 31),
> + .cfg_int_stat0 = REG_FIELD(DSI_INT_ST0, 0, 20),
> + .cfg_int_stat1 = REG_FIELD(DSI_INT_ST1, 0, 12),
> + .cfg_int_mask0 = REG_FIELD(DSI_INT_MSK0, 0, 20),
> + .cfg_int_mask1 = REG_FIELD(DSI_INT_MSK1, 0, 12),
> + .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR, 0, 23),
> .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
> };
>
> @@ -382,7 +382,7 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
> .cfg_cmd_mode_gen_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 11, 11),
> .cfg_cmd_mode_dcs_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 12, 12),
> .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 13, 13),
> - .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 14),
> + .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 6),
> .cfg_vid_mode_en = REG_FIELD(DSI_VID_MODE_CFG_V101, 0, 0),
> .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG_V101, 1, 2),
> .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG_V101, 3, 8),
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next prev parent reply other threads:[~2020-06-10 12:22 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-09 17:49 [PATCH v9 00/11] Genericize DW MIPI DSI bridge and add i.MX 6 driver Adrian Ratiu
2020-06-09 17:49 ` [PATCH v9 01/11] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure Adrian Ratiu
2020-06-09 17:49 ` [PATCH v9 02/11] drm: bridge: dw_mipi_dsi: abstract register access using reg_fields Adrian Ratiu
2020-06-09 17:49 ` [PATCH v9 03/11] drm: bridge: dw_mipi_dsi: add dsi v1.01 support Adrian Ratiu
[not found] ` <20200609174959.955926-4-adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2020-06-10 12:20 ` Yannick FERTRE
2020-06-09 17:49 ` [PATCH v9 04/11] drm: bridge: dw_mipi_dsi: remove bind/unbind API Adrian Ratiu
[not found] ` <20200609174959.955926-5-adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2020-06-10 12:21 ` Yannick FERTRE
2020-06-09 17:49 ` [PATCH v9 07/11] drm: imx: Add i.MX 6 MIPI DSI host platform driver Adrian Ratiu
2020-06-09 17:49 ` [PATCH v9 08/11] drm: stm: dw-mipi-dsi: let the bridge handle the HW version check Adrian Ratiu
2020-06-09 17:49 ` [PATCH v9 09/11] drm: bridge: dw-mipi-dsi: split low power cfg register into fields Adrian Ratiu
[not found] ` <20200609174959.955926-10-adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2020-06-10 12:21 ` Yannick FERTRE
2020-06-09 17:49 ` [PATCH v9 10/11] drm: bridge: dw-mipi-dsi: fix bad register field offsets Adrian Ratiu
[not found] ` <20200609174959.955926-11-adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2020-06-10 12:22 ` Yannick FERTRE [this message]
2020-06-09 17:49 ` [PATCH v9 11/11] Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan Adrian Ratiu
[not found] ` <20200609174959.955926-1-adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2020-06-09 17:49 ` [PATCH v9 05/11] dt-bindings: display: add i.MX6 MIPI DSI host controller doc Adrian Ratiu
[not found] ` <20200609174959.955926-6-adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2020-06-12 21:11 ` Rob Herring
2020-06-09 17:49 ` [PATCH v9 06/11] ARM: dts: imx6qdl: add missing mipi dsi properties Adrian Ratiu
2020-06-29 8:47 ` [PATCH v9 00/11] Genericize DW MIPI DSI bridge and add i.MX 6 driver Neil Armstrong
[not found] ` <c6f10db1-7f56-a156-36a1-125e764c8c1a-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2020-07-01 6:35 ` Adrian Ratiu
[not found] ` <87lfk3kaj4.fsf-Hx0R3YBcjnrrDJPETb4MAhUsoSCIEsfjNWc2n73sL8y+gHQt+EBHu/rpjleITZ0KWu6Lckefmi4@public.gmane.org>
2020-07-01 7:50 ` Neil Armstrong
2020-08-15 13:05 ` Ezequiel Garcia
2020-08-24 9:47 ` Neil Armstrong
2020-09-15 13:05 ` Neil Armstrong
2020-10-23 15:32 ` Adrian Ratiu
2020-07-01 12:50 ` Heiko Stübner
2020-07-01 20:32 ` Adrian Ratiu
-- strict thread matches above, loose matches on Subject: below --
2020-06-09 16:26 Adrian Ratiu
[not found] ` <20200609162700.953260-1-adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2020-06-09 16:26 ` [PATCH v9 10/11] drm: bridge: dw-mipi-dsi: fix bad register field offsets Adrian Ratiu
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