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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v2_03/10=5D_phy=3A_rockchip=3A_naneng-?= =?US-ASCII?Q?combphy=3A_add_SGMII_MAC_selection_for_RK3568?= User-Agent: K-9 Mail for Android In-Reply-To: <0cf1f734-69d4-471f-aa22-e1a2e7d0341b@lunn.ch> References: <20260801142244.679437-2-coiaprant@gmail.com> <20260801142244.679437-5-coiaprant@gmail.com> <0cf1f734-69d4-471f-aa22-e1a2e7d0341b@lunn.ch> Message-ID: <7F609DE6-F3C6-487E-9113-449F5BE05D94@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260801_202825_989913_B738FF80 X-CRM114-Status: GOOD ( 15.20 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org On August 2, 2026 4:58:39 AM GMT+08:00, Andrew Lunn wrote: >On Sat, Aug 01, 2026 at 10:22:27PM +0800, Coia Prant wrote: >> On RK3568, the SGMII interface can be routed to either GMAC0 or >> GMAC1 via the GRF register pipe_sgmii_mac_sel. >> >> Add support for this selection by introducing >> the "rockchip,sgmii-mac-sel" DT property. >> >> The hardware reset value is GMAC1 (1). If the property is set to 0, >> the driver routes SGMII to GMAC0; if set to 1 (or omitted), it >> remains at GMAC1. >> >> This is necessary for boards such as the Ariaboard Photonicat, which >> uses the SGMII interface connected to GMAC0. > >If SGMII is not selected, what MII is used? RGMII? > >Can this setting be implied from phy-mode? > > Andrew Hi Andrew, If phy-mode is not "sgmii" (e.g., "rgmii" or "rmii"), the GMAC works in the corresponding mode and this register is not touched. The reset default (GMAC1) remains, but it has no effect in non-SGMII modes because the register only controls SGMII signal routing. Regarding inference from phy-mode: phy-mode = "sgmii" only tells the MAC driver that the interface is SGMII. It does not specify whether the SGMII signals are physically routed to GMAC0 or GMAC1 on the board. That routing is a board-level decision and cannot be derived from any other DT property. Also, the PHY (Naneng Combo PHY) is initialized by the XPCS glue driver (pcs-xpcs-rk), not by the GMAC driver. The PHY driver has no way to know which GMAC is using it. Making the PHY aware of the MAC ID would require significant changes to the PHY layer, which is out of scope for this series. Therefore, an explicit DT property is the cleanest and most maintainable way to describe this hardware routing. Thanks, Coia _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip