[RFC PATCH v1 2/6] dt-bindings: phy: rockchip: add rk3328 usb3 phy

Peter Geis
2025-01-15T01:29:18Z

Add documentation for the usb3 phy as implemented on the rk3328 SoC.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---

.../bindings/phy/rockchip,inno-usb3phy.yaml | 166 ++++++++++++++++++
1 file changed, 166 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip,inno-usb3phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb3phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb3phy.yaml
new file mode 100644
index 000000000000..cde489ca87ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb3phy.yaml
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/rockchip,inno-usb3phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip USB 3.0 phy with Innosilicon IP block
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3328-usb3phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 3
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: refclk-usb3otg
+ - const: usb3phy-otg
+ - const: usb3phy-pipe
+
+ interrupts:
+ minItems: 4
+
+ interrupt-names:
+ items:
+ - const: bvalid
+ - const: id
+ - const: linestate
+ - const: rxdet
+
+ resets:
+ minItems: 6
+
+ reset-names:
+ items:
+ - const: usb3phy-u2-por
+ - const: usb3phy-u3-por
+ - const: usb3phy-pipe-mac
+ - const: usb3phy-utmi-mac
+ - const: usb3phy-utmi-apb
+ - const: usb3phy-pipe-apb
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+patternProperties:
+
+ utmi-port@[0-9a-f]+$:
+ type: object
+ additionalProperties: false
+
+ properties:
+ compatible:
+ enum:
+ - rockchip,rk3328-usb3phy-utmi
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ phy-supply:
+ description:
+ Phandle to a regulator that provides power to VBUS.
+ See ./phy-bindings.txt for details.
+
+ required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+ pipe-port@[0-9a-f]+$:
+ type: object
+ additionalProperties: false
+
+ properties:
+ compatible:
+ enum:
+ - rockchip,rk3328-usb3phy-pipe
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ phy-supply:
+ description:
+ Phandle to a regulator that provides power to VBUS.
+ See ./phy-bindings.txt for details.
+
+ required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3328-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb3phy: usb3-phy@ff460000 {
+ compatible = "rockchip,rk3328-usb3phy";
+ reg = <0x0 0xff460000 0x0 0x10000>;
+ clocks = <&cru SCLK_REF_USB3OTG>, <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
+ clock-names = "refclk-usb3otg", "usb3phy-otg", "usb3phy-pipe";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bvalid", "id", "linestate", "rxdet";
+ resets = <&cru SRST_USB3PHY_U2>,
+ <&cru SRST_USB3PHY_U3>,
+ <&cru SRST_USB3PHY_PIPE>,
+ <&cru SRST_USB3OTG_UTMI>,
+ <&cru SRST_USB3PHY_OTG_P>,
+ <&cru SRST_USB3PHY_PIPE_P>;
+ reset-names = "usb3phy-u2-por", "usb3phy-u3-por",
+ "usb3phy-pipe-mac", "usb3phy-utmi-mac",
+ "usb3phy-utmi-apb", "usb3phy-pipe-apb";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ usb3phy_utmi: utmi-port@ff470000 {
+ compatible = "rockchip,rk3328-usb3phy-utmi";
+ reg = <0x0 0xff470000 0x0 0x8000>;
+ #phy-cells = <0>;
+ };
+
+ usb3phy_pipe: pipe-port@ff478000 {
+ compatible = "rockchip,rk3328-usb3phy-pipe";
+ reg = <0x0 0xff478000 0x0 0x8000>;
+ #phy-cells = <0>;
+ };
+ };
+ };
--
2.39.5