[PATCH v6 0/8] Genericize DW MIPI DSI bridge and add i.MX 6 driver

[PATCH v6 0/8] Genericize DW MIPI DSI bridge and add i.MX 6 driver

[Adrian Ratiu]

Hello everyone,

Many thanks to all who have contributed to this new iteration,
especially to Arnaud Ferraris for his stm32mp1 testing and to
Adrian Pop for his stm32f7 testing & debugging help.

Further testing, especially on Rockchip devices, is very much
appreciated.

All reported issues have been addressed and this series should
apply cleanly on latest next-20200414 tree.

Tested on imx6dl, stm32mp1 and stm32f7.

Best wishes,
Adrian

Adrian Ratiu (8):
  drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
  drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
  drm: bridge: synopsis: add dsi v1.01 support
  drm: imx: Add i.MX 6 MIPI DSI host platform driver
  dt-bindings: display: add i.MX6 MIPI DSI host controller doc
  drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
  drm: bridge: dw-mipi-dsi: split low power cfg register into fields
  drm: bridge: dw-mipi-dsi: fix bad register field offsets

 .../display/imx/fsl,mipi-dsi-imx6.yaml        | 139 ++++
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 691 +++++++++++++-----
 drivers/gpu/drm/imx/Kconfig                   |   7 +
 drivers/gpu/drm/imx/Makefile                  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c        | 409 +++++++++++
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c         |  12 +-
 6 files changed, 1050 insertions(+), 209 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

-- 
2.26.0

[PATCH v6 1/8] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

[Adrian Ratiu]

In order to support multiple versions of the Synopsis MIPI DSI host
controller, which have different register layouts but almost identical
HW protocols, we add a regmap infrastructure which can abstract away
register accesses for platform drivers using the bridge.

The controller HW revision is detected during bridge probe which will
be used in future commits to load the relevant register layout which
the bridge will use transparently to the platform drivers.

Suggested-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Adrian Pop <pop.adrian61@gmail.com>
Tested-by: Arnaud Ferraris <arnaud.ferraris@collabora.com>
Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.com>
---
New in v5.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208 ++++++++++--------
 1 file changed, 117 insertions(+), 91 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5ef0f154aa7b..6d9e2f21c9cc 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/of_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/regmap.h>
 #include <linux/reset.h>
 
 #include <video/mipi_display.h>
@@ -227,6 +228,7 @@ struct dw_mipi_dsi {
 	struct drm_bridge *panel_bridge;
 	struct device *dev;
 	void __iomem *base;
+	struct regmap *regs;
 
 	struct clk *pclk;
 
@@ -235,6 +237,7 @@ struct dw_mipi_dsi {
 	u32 lanes;
 	u32 format;
 	unsigned long mode_flags;
+	u32 hw_version;
 
 #ifdef CONFIG_DEBUG_FS
 	struct dentry *debugfs;
@@ -249,6 +252,13 @@ struct dw_mipi_dsi {
 	const struct dw_mipi_dsi_plat_data *plat_data;
 };
 
+static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.name = "dw-mipi-dsi",
+};
+
 /*
  * Check if either a link to a master or slave is present
  */
@@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
 	return container_of(bridge, struct dw_mipi_dsi, bridge);
 }
 
-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
-{
-	writel(val, dsi->base + reg);
-}
-
-static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
-{
-	return readl(dsi->base + reg);
-}
-
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 				   struct mipi_dsi_device *device)
 {
@@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 	if (lpm)
 		val |= CMD_MODE_ALL_LP;
 
-	dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
-	dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+	regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+	regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 {
 	int ret;
-	u32 val, mask;
+	u32 val = 0, mask;
 
-	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-				 val, !(val & GEN_CMD_FULL), 1000,
-				 CMD_PKT_STATUS_TIMEOUT_US);
+	ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+				       val, !(val & GEN_CMD_FULL), 1000,
+				       CMD_PKT_STATUS_TIMEOUT_US);
 	if (ret) {
 		dev_err(dsi->dev, "failed to get available command FIFO\n");
 		return ret;
 	}
 
-	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+	regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
 
 	mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-				 val, (val & mask) == mask,
-				 1000, CMD_PKT_STATUS_TIMEOUT_US);
+	ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+				       val, (val & mask) == mask,
+				       1000, CMD_PKT_STATUS_TIMEOUT_US);
 	if (ret) {
 		dev_err(dsi->dev, "failed to write command FIFO\n");
 		return ret;
@@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
 	const u8 *tx_buf = packet->payload;
 	int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
 	__le32 word;
-	u32 val;
+	u32 val = 0;
 
 	while (len) {
 		if (len < pld_data_bytes) {
 			word = 0;
 			memcpy(&word, tx_buf, len);
-			dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
+			regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
+				     le32_to_cpu(word));
 			len = 0;
 		} else {
 			memcpy(&word, tx_buf, pld_data_bytes);
-			dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
+			regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
+				     le32_to_cpu(word));
 			tx_buf += pld_data_bytes;
 			len -= pld_data_bytes;
 		}
 
-		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-					 val, !(val & GEN_PLD_W_FULL), 1000,
-					 CMD_PKT_STATUS_TIMEOUT_US);
+		ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+					       val, !(val & GEN_PLD_W_FULL),
+					       1000, CMD_PKT_STATUS_TIMEOUT_US);
 		if (ret) {
 			dev_err(dsi->dev,
 				"failed to get available write payload FIFO\n");
@@ -438,12 +440,12 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
 {
 	int i, j, ret, len = msg->rx_len;
 	u8 *buf = msg->rx_buf;
-	u32 val;
+	u32 val = 0;
 
 	/* Wait end of the read operation */
-	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-				 val, !(val & GEN_RD_CMD_BUSY),
-				 1000, CMD_PKT_STATUS_TIMEOUT_US);
+	ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+				       val, !(val & GEN_RD_CMD_BUSY),
+				       1000, CMD_PKT_STATUS_TIMEOUT_US);
 	if (ret) {
 		dev_err(dsi->dev, "Timeout during read operation\n");
 		return ret;
@@ -451,15 +453,15 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
 
 	for (i = 0; i < len; i += 4) {
 		/* Read fifo must not be empty before all bytes are read */
-		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-					 val, !(val & GEN_PLD_R_EMPTY),
-					 1000, CMD_PKT_STATUS_TIMEOUT_US);
+		ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+					       val, !(val & GEN_PLD_R_EMPTY),
+					       1000, CMD_PKT_STATUS_TIMEOUT_US);
 		if (ret) {
 			dev_err(dsi->dev, "Read payload FIFO is empty\n");
 			return ret;
 		}
 
-		val = dsi_read(dsi, DSI_GEN_PLD_DATA);
+		regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val);
 		for (j = 0; j < 4 && j + i < len; j++)
 			buf[i + j] = val >> (8 * j);
 	}
@@ -536,29 +538,29 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 	}
 #endif /* CONFIG_DEBUG_FS */
 
-	dsi_write(dsi, DSI_VID_MODE_CFG, val);
+	regmap_write(dsi->regs, DSI_VID_MODE_CFG, val);
 }
 
 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 				 unsigned long mode_flags)
 {
-	dsi_write(dsi, DSI_PWR_UP, RESET);
+	regmap_write(dsi->regs, DSI_PWR_UP, RESET);
 
 	if (mode_flags & MIPI_DSI_MODE_VIDEO) {
-		dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
+		regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 		dw_mipi_dsi_video_mode_config(dsi);
-		dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
+		regmap_write(dsi->regs, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 	} else {
-		dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
+		regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
 	}
 
-	dsi_write(dsi, DSI_PWR_UP, POWERUP);
+	regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
 }
 
 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 {
-	dsi_write(dsi, DSI_PWR_UP, RESET);
-	dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
+	regmap_write(dsi->regs, DSI_PWR_UP, RESET);
+	regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ);
 }
 
 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
@@ -573,14 +575,14 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 	 */
 	u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
 
-	dsi_write(dsi, DSI_PWR_UP, RESET);
+	regmap_write(dsi->regs, DSI_PWR_UP, RESET);
 
 	/*
 	 * TODO dw drv improvements
 	 * timeout clock division should be computed with the
 	 * high speed transmission counter timeout and byte lane...
 	 */
-	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
+	regmap_write(dsi->regs, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
 		  TX_ESC_CLK_DIVISION(esc_clk_division));
 }
 
@@ -609,22 +611,22 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 		val |= HSYNC_ACTIVE_LOW;
 
-	dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
-	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
-	dsi_write(dsi, DSI_DPI_CFG_POL, val);
+	regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel));
+	regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color);
+	regmap_write(dsi->regs, DSI_DPI_CFG_POL, val);
 	/*
 	 * TODO dw drv improvements
 	 * largest packet sizes during hfp or during vsa/vpb/vfp
 	 * should be computed according to byte lane, lane number and only
 	 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
 	 */
-	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
+	regmap_write(dsi->regs, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 		  | INVACT_LPCMD_TIME(4));
 }
 
 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 {
-	dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
+	regmap_write(dsi->regs, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
 }
 
 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
@@ -638,7 +640,7 @@ static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 	 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
 	 */
 
-	dsi_write(dsi, DSI_VID_PKT_SIZE,
+	regmap_write(dsi->regs, DSI_VID_PKT_SIZE,
 		       dw_mipi_is_dual_mode(dsi) ?
 				VID_PKT_SIZE(mode->hdisplay / 2) :
 				VID_PKT_SIZE(mode->hdisplay));
@@ -651,14 +653,15 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 	 * compute high speed transmission counter timeout according
 	 * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
 	 */
-	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
+	regmap_write(dsi->regs, DSI_TO_CNT_CFG,
+		     HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 	/*
 	 * TODO dw drv improvements
 	 * the Bus-Turn-Around Timeout Counter should be computed
 	 * according to byte lane...
 	 */
-	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
-	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
+	regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00);
+	regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
 }
 
 /* Get lane byte clock cycles. */
@@ -692,13 +695,13 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
 	 * computations below may be improved...
 	 */
 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
-	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
+	regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc);
 
 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
-	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
+	regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc);
 
 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
-	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
+	regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc);
 }
 
 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
@@ -711,10 +714,10 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
 	vfp = mode->vsync_start - mode->vdisplay;
 	vbp = mode->vtotal - mode->vsync_end;
 
-	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
-	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
-	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
-	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
+	regmap_write(dsi->regs, DSI_VID_VACTIVE_LINES, vactive);
+	regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa);
+	regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp);
+	regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp);
 }
 
 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
@@ -737,23 +740,25 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 	 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
 	 */
 
-	hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
+	regmap_read(dsi->regs, DSI_VERSION, &hw_version);
+	hw_version &= VERSION;
 
 	if (hw_version >= HWVER_131) {
-		dsi_write(dsi, DSI_PHY_TMR_CFG,
-			  PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
-			  PHY_LP2HS_TIME_V131(timing.data_lp2hs));
-		dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
+		regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
+			     PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
+			     PHY_LP2HS_TIME_V131(timing.data_lp2hs));
+		regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG,
+			     MAX_RD_TIME_V131(10000));
 	} else {
-		dsi_write(dsi, DSI_PHY_TMR_CFG,
-			  PHY_HS2LP_TIME(timing.data_hs2lp) |
-			  PHY_LP2HS_TIME(timing.data_lp2hs) |
-			  MAX_RD_TIME(10000));
+		regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
+			     PHY_HS2LP_TIME(timing.data_hs2lp) |
+			     PHY_LP2HS_TIME(timing.data_lp2hs) |
+			     MAX_RD_TIME(10000));
 	}
 
-	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
-		  PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
-		  PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
+	regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG,
+		     PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
+		     PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
 }
 
 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
@@ -763,46 +768,49 @@ static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 	 * stop wait time should be the maximum between host dsi
 	 * and panel stop wait times
 	 */
-	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
-		  N_LANES(dsi->lanes));
+	regmap_write(dsi->regs, DSI_PHY_IF_CFG,
+		     PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes));
 }
 
 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
 {
 	/* Clear PHY state */
-	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
-		  | PHY_RSTZ | PHY_SHUTDOWNZ);
-	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
-	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
-	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+	regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
+		     | PHY_RSTZ | PHY_SHUTDOWNZ);
+	regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+	regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
+	regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 }
 
 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
 {
-	u32 val;
+	u32 val = 0;
 	int ret;
 
-	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
-		  PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
+	regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
+		     PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 
-	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
-				 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
+	ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
+				       val, val & PHY_LOCK,
+				       1000, PHY_STATUS_TIMEOUT_US);
 	if (ret)
 		DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
 
-	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
-				 val, val & PHY_STOP_STATE_CLK_LANE, 1000,
-				 PHY_STATUS_TIMEOUT_US);
+	ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
+				       val, val & PHY_STOP_STATE_CLK_LANE, 1000,
+				       PHY_STATUS_TIMEOUT_US);
 	if (ret)
 		DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
 }
 
 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 {
-	dsi_read(dsi, DSI_INT_ST0);
-	dsi_read(dsi, DSI_INT_ST1);
-	dsi_write(dsi, DSI_INT_MSK0, 0);
-	dsi_write(dsi, DSI_INT_MSK1, 0);
+	u32 val;
+
+	regmap_read(dsi->regs, DSI_INT_ST0, &val);
+	regmap_read(dsi->regs, DSI_INT_ST1, &val);
+	regmap_write(dsi->regs, DSI_INT_MSK0, 0);
+	regmap_write(dsi->regs, DSI_INT_MSK1, 0);
 }
 
 static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
@@ -989,6 +997,14 @@ static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
 
 #endif /* CONFIG_DEBUG_FS */
 
+static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi *dsi)
+{
+	regmap_read(dsi->regs, DSI_VERSION, &dsi->hw_version);
+	dsi->hw_version &= VERSION;
+	if (!dsi->hw_version)
+		dev_err(dsi->dev, "Failed to read DSI hw version register\n");
+}
+
 static struct dw_mipi_dsi *
 __dw_mipi_dsi_probe(struct platform_device *pdev,
 		    const struct dw_mipi_dsi_plat_data *plat_data)
@@ -1020,6 +1036,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
 		dsi->base = plat_data->base;
 	}
 
+	dsi->regs = devm_regmap_init_mmio(dev, dsi->base,
+					  &dw_mipi_dsi_regmap_cfg);
+	if (IS_ERR(dsi->regs)) {
+		ret = PTR_ERR(dsi->regs);
+		DRM_ERROR("Failed to create DW MIPI DSI regmap: %d\n", ret);
+		return ERR_PTR(ret);
+	}
+
 	dsi->pclk = devm_clk_get(dev, "pclk");
 	if (IS_ERR(dsi->pclk)) {
 		ret = PTR_ERR(dsi->pclk);
@@ -1055,6 +1079,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
 		clk_disable_unprepare(dsi->pclk);
 	}
 
+	dw_mipi_dsi_get_hw_version(dsi);
+
 	dw_mipi_dsi_debugfs_init(dsi);
 	pm_runtime_enable(dev);
 
-- 
2.26.0

Re: [PATCH v6 1/8] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

[Enric Balletbo Serra]

Hi Adrian,

Some few comments/nits below,

Missatge de Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> del dia dt., 14
d’abr. 2020 a les 17:19:
>
> In order to support multiple versions of the Synopsis MIPI DSI host
> controller, which have different register layouts but almost identical
> HW protocols, we add a regmap infrastructure which can abstract away
> register accesses for platform drivers using the bridge.
>
> The controller HW revision is detected during bridge probe which will
> be used in future commits to load the relevant register layout which
> the bridge will use transparently to the platform drivers.
>
> Suggested-by: Ezequiel Garcia <ezequiel-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Tested-by: Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Signed-off-by: Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> ---
> New in v5.
> ---
>  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208 ++++++++++--------
>  1 file changed, 117 insertions(+), 91 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 5ef0f154aa7b..6d9e2f21c9cc 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -15,6 +15,7 @@
>  #include <linux/module.h>
>  #include <linux/of_device.h>
>  #include <linux/pm_runtime.h>
> +#include <linux/regmap.h>

Should Kconfig select REGMAP for this driver?

>  #include <linux/reset.h>
>
>  #include <video/mipi_display.h>
> @@ -227,6 +228,7 @@ struct dw_mipi_dsi {
>         struct drm_bridge *panel_bridge;
>         struct device *dev;
>         void __iomem *base;
> +       struct regmap *regs;
>
>         struct clk *pclk;
>
> @@ -235,6 +237,7 @@ struct dw_mipi_dsi {
>         u32 lanes;
>         u32 format;
>         unsigned long mode_flags;
> +       u32 hw_version;
>
>  #ifdef CONFIG_DEBUG_FS
>         struct dentry *debugfs;
> @@ -249,6 +252,13 @@ struct dw_mipi_dsi {
>         const struct dw_mipi_dsi_plat_data *plat_data;
>  };
>
> +static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
> +       .reg_bits = 32,
> +       .val_bits = 32,
> +       .reg_stride = 4,
> +       .name = "dw-mipi-dsi",
> +};
> +
>  /*
>   * Check if either a link to a master or slave is present
>   */
> @@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
>         return container_of(bridge, struct dw_mipi_dsi, bridge);
>  }
>
> -static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
> -{
> -       writel(val, dsi->base + reg);
> -}
> -
> -static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
> -{
> -       return readl(dsi->base + reg);
> -}
> -
>  static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
>                                    struct mipi_dsi_device *device)
>  {
> @@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
>         if (lpm)
>                 val |= CMD_MODE_ALL_LP;
>
> -       dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
> -       dsi_write(dsi, DSI_CMD_MODE_CFG, val);
> +       regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
> +       regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
>  }
>
>  static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
>  {
>         int ret;
> -       u32 val, mask;
> +       u32 val = 0, mask;
>

I think that this change is not needed, `val` is an input variable
that will be overwritten inside the regmap_read_poll_timeout.
Initialize here is not needed.

> -       ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> -                                val, !(val & GEN_CMD_FULL), 1000,
> -                                CMD_PKT_STATUS_TIMEOUT_US);
> +       ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> +                                      val, !(val & GEN_CMD_FULL), 1000,
> +                                      CMD_PKT_STATUS_TIMEOUT_US);
>         if (ret) {
>                 dev_err(dsi->dev, "failed to get available command FIFO\n");
>                 return ret;
>         }
>
> -       dsi_write(dsi, DSI_GEN_HDR, hdr_val);
> +       regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
>
>         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
> -       ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> -                                val, (val & mask) == mask,
> -                                1000, CMD_PKT_STATUS_TIMEOUT_US);
> +       ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> +                                      val, (val & mask) == mask,
> +                                      1000, CMD_PKT_STATUS_TIMEOUT_US);
>         if (ret) {
>                 dev_err(dsi->dev, "failed to write command FIFO\n");
>                 return ret;
> @@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
>         const u8 *tx_buf = packet->payload;
>         int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
>         __le32 word;
> -       u32 val;
> +       u32 val = 0;
>

The same here, 'val' is used for the regmap_read_poll_timeout and will
be overwritten, no need to initialize.

>         while (len) {
>                 if (len < pld_data_bytes) {
>                         word = 0;
>                         memcpy(&word, tx_buf, len);
> -                       dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
> +                       regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
> +                                    le32_to_cpu(word));
>                         len = 0;
>                 } else {
>                         memcpy(&word, tx_buf, pld_data_bytes);
> -                       dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
> +                       regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
> +                                    le32_to_cpu(word));
>                         tx_buf += pld_data_bytes;
>                         len -= pld_data_bytes;
>                 }
>
> -               ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> -                                        val, !(val & GEN_PLD_W_FULL), 1000,
> -                                        CMD_PKT_STATUS_TIMEOUT_US);
> +               ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> +                                              val, !(val & GEN_PLD_W_FULL),
> +                                              1000, CMD_PKT_STATUS_TIMEOUT_US);
>                 if (ret) {
>                         dev_err(dsi->dev,
>                                 "failed to get available write payload FIFO\n");
> @@ -438,12 +440,12 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
>  {
>         int i, j, ret, len = msg->rx_len;
>         u8 *buf = msg->rx_buf;
> -       u32 val;
> +       u32 val = 0;
>

ditto

>         /* Wait end of the read operation */
> -       ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> -                                val, !(val & GEN_RD_CMD_BUSY),
> -                                1000, CMD_PKT_STATUS_TIMEOUT_US);
> +       ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> +                                      val, !(val & GEN_RD_CMD_BUSY),
> +                                      1000, CMD_PKT_STATUS_TIMEOUT_US);
>         if (ret) {
>                 dev_err(dsi->dev, "Timeout during read operation\n");
>                 return ret;
> @@ -451,15 +453,15 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
>
>         for (i = 0; i < len; i += 4) {
>                 /* Read fifo must not be empty before all bytes are read */
> -               ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> -                                        val, !(val & GEN_PLD_R_EMPTY),
> -                                        1000, CMD_PKT_STATUS_TIMEOUT_US);
> +               ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> +                                              val, !(val & GEN_PLD_R_EMPTY),
> +                                              1000, CMD_PKT_STATUS_TIMEOUT_US);
>                 if (ret) {
>                         dev_err(dsi->dev, "Read payload FIFO is empty\n");
>                         return ret;
>                 }
>
> -               val = dsi_read(dsi, DSI_GEN_PLD_DATA);
> +               regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val);
>                 for (j = 0; j < 4 && j + i < len; j++)
>                         buf[i + j] = val >> (8 * j);
>         }
> @@ -536,29 +538,29 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
>         }
>  #endif /* CONFIG_DEBUG_FS */
>
> -       dsi_write(dsi, DSI_VID_MODE_CFG, val);
> +       regmap_write(dsi->regs, DSI_VID_MODE_CFG, val);
>  }
>
>  static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
>                                  unsigned long mode_flags)
>  {
> -       dsi_write(dsi, DSI_PWR_UP, RESET);
> +       regmap_write(dsi->regs, DSI_PWR_UP, RESET);
>
>         if (mode_flags & MIPI_DSI_MODE_VIDEO) {
> -               dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
> +               regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
>                 dw_mipi_dsi_video_mode_config(dsi);
> -               dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
> +               regmap_write(dsi->regs, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
>         } else {
> -               dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> +               regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
>         }
>
> -       dsi_write(dsi, DSI_PWR_UP, POWERUP);
> +       regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
>  }
>
>  static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
>  {
> -       dsi_write(dsi, DSI_PWR_UP, RESET);
> -       dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
> +       regmap_write(dsi->regs, DSI_PWR_UP, RESET);
> +       regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ);
>  }
>
>  static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
> @@ -573,14 +575,14 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
>          */
>         u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
>
> -       dsi_write(dsi, DSI_PWR_UP, RESET);
> +       regmap_write(dsi->regs, DSI_PWR_UP, RESET);
>
>         /*
>          * TODO dw drv improvements
>          * timeout clock division should be computed with the
>          * high speed transmission counter timeout and byte lane...
>          */
> -       dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
> +       regmap_write(dsi->regs, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
>                   TX_ESC_CLK_DIVISION(esc_clk_division));
>  }
>
> @@ -609,22 +611,22 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
>         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
>                 val |= HSYNC_ACTIVE_LOW;
>
> -       dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
> -       dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
> -       dsi_write(dsi, DSI_DPI_CFG_POL, val);
> +       regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel));
> +       regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color);
> +       regmap_write(dsi->regs, DSI_DPI_CFG_POL, val);
>         /*
>          * TODO dw drv improvements
>          * largest packet sizes during hfp or during vsa/vpb/vfp
>          * should be computed according to byte lane, lane number and only
>          * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
>          */
> -       dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
> +       regmap_write(dsi->regs, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
>                   | INVACT_LPCMD_TIME(4));
>  }
>
>  static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
>  {
> -       dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
> +       regmap_write(dsi->regs, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
>  }
>
>  static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
> @@ -638,7 +640,7 @@ static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
>          * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
>          */
>
> -       dsi_write(dsi, DSI_VID_PKT_SIZE,
> +       regmap_write(dsi->regs, DSI_VID_PKT_SIZE,
>                        dw_mipi_is_dual_mode(dsi) ?
>                                 VID_PKT_SIZE(mode->hdisplay / 2) :
>                                 VID_PKT_SIZE(mode->hdisplay));
> @@ -651,14 +653,15 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
>          * compute high speed transmission counter timeout according
>          * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
>          */
> -       dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
> +       regmap_write(dsi->regs, DSI_TO_CNT_CFG,
> +                    HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
>         /*
>          * TODO dw drv improvements
>          * the Bus-Turn-Around Timeout Counter should be computed
>          * according to byte lane...
>          */
> -       dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
> -       dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> +       regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00);
> +       regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
>  }
>
>  /* Get lane byte clock cycles. */
> @@ -692,13 +695,13 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
>          * computations below may be improved...
>          */
>         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
> -       dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
> +       regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc);
>
>         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
> -       dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
> +       regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc);
>
>         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
> -       dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
> +       regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc);
>  }
>
>  static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
> @@ -711,10 +714,10 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
>         vfp = mode->vsync_start - mode->vdisplay;
>         vbp = mode->vtotal - mode->vsync_end;
>
> -       dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
> -       dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
> -       dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
> -       dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
> +       regmap_write(dsi->regs, DSI_VID_VACTIVE_LINES, vactive);
> +       regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa);
> +       regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp);
> +       regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp);
>  }
>
>  static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
> @@ -737,23 +740,25 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
>          * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
>          */
>
> -       hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
> +       regmap_read(dsi->regs, DSI_VERSION, &hw_version);
> +       hw_version &= VERSION;

If I am not wrong, you already introduced a function to get the
hardware version and is stored in dsi->hw_version. Maybe you could you
use that variable and remove that code.

>
>         if (hw_version >= HWVER_131) {
> -               dsi_write(dsi, DSI_PHY_TMR_CFG,
> -                         PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
> -                         PHY_LP2HS_TIME_V131(timing.data_lp2hs));
> -               dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
> +               regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
> +                            PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
> +                            PHY_LP2HS_TIME_V131(timing.data_lp2hs));
> +               regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG,
> +                            MAX_RD_TIME_V131(10000));
>         } else {
> -               dsi_write(dsi, DSI_PHY_TMR_CFG,
> -                         PHY_HS2LP_TIME(timing.data_hs2lp) |
> -                         PHY_LP2HS_TIME(timing.data_lp2hs) |
> -                         MAX_RD_TIME(10000));
> +               regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
> +                            PHY_HS2LP_TIME(timing.data_hs2lp) |
> +                            PHY_LP2HS_TIME(timing.data_lp2hs) |
> +                            MAX_RD_TIME(10000));
>         }
>
> -       dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
> -                 PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
> -                 PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
> +       regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG,
> +                    PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
> +                    PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
>  }
>
>  static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> @@ -763,46 +768,49 @@ static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
>          * stop wait time should be the maximum between host dsi
>          * and panel stop wait times
>          */
> -       dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
> -                 N_LANES(dsi->lanes));
> +       regmap_write(dsi->regs, DSI_PHY_IF_CFG,
> +                    PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes));
>  }
>
>  static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
>  {
>         /* Clear PHY state */
> -       dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
> -                 | PHY_RSTZ | PHY_SHUTDOWNZ);
> -       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> -       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
> -       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> +       regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
> +                    | PHY_RSTZ | PHY_SHUTDOWNZ);
> +       regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> +       regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
> +       regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>  }
>
>  static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
>  {
> -       u32 val;
> +       u32 val = 0;

ditto

>         int ret;
>
> -       dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
> -                 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
> +       regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
> +                    PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
>
> -       ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
> -                                val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
> +       ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
> +                                      val, val & PHY_LOCK,
> +                                      1000, PHY_STATUS_TIMEOUT_US);
>         if (ret)
>                 DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
>
> -       ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
> -                                val, val & PHY_STOP_STATE_CLK_LANE, 1000,
> -                                PHY_STATUS_TIMEOUT_US);
> +       ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
> +                                      val, val & PHY_STOP_STATE_CLK_LANE, 1000,
> +                                      PHY_STATUS_TIMEOUT_US);
>         if (ret)
>                 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
>  }
>
>  static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
>  {
> -       dsi_read(dsi, DSI_INT_ST0);
> -       dsi_read(dsi, DSI_INT_ST1);
> -       dsi_write(dsi, DSI_INT_MSK0, 0);
> -       dsi_write(dsi, DSI_INT_MSK1, 0);
> +       u32 val;
> +
> +       regmap_read(dsi->regs, DSI_INT_ST0, &val);
> +       regmap_read(dsi->regs, DSI_INT_ST1, &val);
> +       regmap_write(dsi->regs, DSI_INT_MSK0, 0);
> +       regmap_write(dsi->regs, DSI_INT_MSK1, 0);
>  }
>
>  static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
> @@ -989,6 +997,14 @@ static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
>
>  #endif /* CONFIG_DEBUG_FS */
>
> +static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi *dsi)
> +{
> +       regmap_read(dsi->regs, DSI_VERSION, &dsi->hw_version);
> +       dsi->hw_version &= VERSION;
> +       if (!dsi->hw_version)
> +               dev_err(dsi->dev, "Failed to read DSI hw version register\n");

Is this an error that should be ignored? If you can't get the HW
version, probably, there is something wrong with your hardware so,
don't you need to return an error?


> +}
> +
>  static struct dw_mipi_dsi *
>  __dw_mipi_dsi_probe(struct platform_device *pdev,
>                     const struct dw_mipi_dsi_plat_data *plat_data)
> @@ -1020,6 +1036,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>                 dsi->base = plat_data->base;
>         }
>
> +       dsi->regs = devm_regmap_init_mmio(dev, dsi->base,
> +                                         &dw_mipi_dsi_regmap_cfg);
> +       if (IS_ERR(dsi->regs)) {
> +               ret = PTR_ERR(dsi->regs);
> +               DRM_ERROR("Failed to create DW MIPI DSI regmap: %d\n", ret);
> +               return ERR_PTR(ret);
> +       }
> +
>         dsi->pclk = devm_clk_get(dev, "pclk");
>         if (IS_ERR(dsi->pclk)) {
>                 ret = PTR_ERR(dsi->pclk);
> @@ -1055,6 +1079,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>                 clk_disable_unprepare(dsi->pclk);
>         }
>
> +       dw_mipi_dsi_get_hw_version(dsi);
> +
>         dw_mipi_dsi_debugfs_init(dsi);
>         pm_runtime_enable(dev);
>
> --
> 2.26.0
>
> _______________________________________________
> dri-devel mailing list
> dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH v6 1/8] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

[Adrian Ratiu]

On Wed, 15 Apr 2020, Enric Balletbo Serra <eballetbo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 
wrote:
> Hi Adrian, 
> 
> Some few comments/nits below, 
> 

Hi Enric,

Thank you for your review, all your suggested changes will be part 
of v7. I have only one minor comment below.

> Missatge de Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> del dia 
> dt., 14 d’abr. 2020 a les 17:19: 
>> 
>> In order to support multiple versions of the Synopsis MIPI DSI 
>> host controller, which have different register layouts but 
>> almost identical HW protocols, we add a regmap infrastructure 
>> which can abstract away register accesses for platform drivers 
>> using the bridge. 
>> 
>> The controller HW revision is detected during bridge probe 
>> which will be used in future commits to load the relevant 
>> register layout which the bridge will use transparently to the 
>> platform drivers. 
>> 
>> Suggested-by: Ezequiel Garcia <ezequiel-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> 
>> Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Tested-by: 
>> Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> Signed-off-by: 
>> Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> --- New in v5.  --- 
>>  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208 
>>  ++++++++++-------- 1 file changed, 117 insertions(+), 91 
>>  deletions(-) 
>> 
>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 
>> 5ef0f154aa7b..6d9e2f21c9cc 100644 --- 
>> a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ 
>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -15,6 +15,7 
>> @@ 
>>  #include <linux/module.h> #include <linux/of_device.h> 
>>  #include <linux/pm_runtime.h> 
>> +#include <linux/regmap.h> 
> 
> Should Kconfig select REGMAP for this driver? 
> 
>>  #include <linux/reset.h> 
>> 
>>  #include <video/mipi_display.h> 
>> @@ -227,6 +228,7 @@ struct dw_mipi_dsi { 
>>         struct drm_bridge *panel_bridge; struct device *dev; 
>>         void __iomem *base; 
>> +       struct regmap *regs; 
>> 
>>         struct clk *pclk; 
>> 
>> @@ -235,6 +237,7 @@ struct dw_mipi_dsi { 
>>         u32 lanes; u32 format; unsigned long mode_flags; 
>> +       u32 hw_version; 
>> 
>>  #ifdef CONFIG_DEBUG_FS 
>>         struct dentry *debugfs; 
>> @@ -249,6 +252,13 @@ struct dw_mipi_dsi { 
>>         const struct dw_mipi_dsi_plat_data *plat_data; 
>>  }; 
>> 
>> +static const struct regmap_config dw_mipi_dsi_regmap_cfg = { + 
>> .reg_bits = 32, +       .val_bits = 32, +       .reg_stride = 
>> 4, +       .name = "dw-mipi-dsi", +}; + 
>>  /* 
>>   * Check if either a link to a master or slave is present */ 
>> @@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi 
>> *bridge_to_dsi(struct drm_bridge *bridge) 
>>         return container_of(bridge, struct dw_mipi_dsi, 
>>         bridge); 
>>  } 
>> 
>> -static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, 
>> u32 val) -{ -       writel(val, dsi->base + reg); -} - -static 
>> inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) -{ - 
>> return readl(dsi->base + reg); -} - 
>>  static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 
>>                                    struct mipi_dsi_device 
>>                                    *device) 
>>  { 
>> @@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct 
>> dw_mipi_dsi *dsi, 
>>         if (lpm) 
>>                 val |= CMD_MODE_ALL_LP; 
>> 
>> -       dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : 
>> PHY_TXREQUESTCLKHS); -       dsi_write(dsi, DSI_CMD_MODE_CFG, 
>> val); +       regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : 
>> PHY_TXREQUESTCLKHS); +       regmap_write(dsi->regs, 
>> DSI_CMD_MODE_CFG, val); 
>>  } 
>> 
>>  static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi 
>>  *dsi, u32 hdr_val) { 
>>         int ret; 
>> -       u32 val, mask; +       u32 val = 0, mask; 
>> 
> 
> I think that this change is not needed, `val` is an input 
> variable that will be overwritten inside the 
> regmap_read_poll_timeout.  Initialize here is not needed. 
> 
>> -       ret = readl_poll_timeout(dsi->base + 
>> DSI_CMD_PKT_STATUS, -                                val, !(val 
>> & GEN_CMD_FULL), 1000, - 
>> CMD_PKT_STATUS_TIMEOUT_US); +       ret = 
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
>> val, !(val & GEN_CMD_FULL), 1000, + 
>> CMD_PKT_STATUS_TIMEOUT_US); 
>>         if (ret) { 
>>                 dev_err(dsi->dev, "failed to get available 
>>                 command FIFO\n"); return ret; 
>>         } 
>> 
>> -       dsi_write(dsi, DSI_GEN_HDR, hdr_val); + 
>> regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val); 
>> 
>>         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 
>> -       ret = readl_poll_timeout(dsi->base + 
>> DSI_CMD_PKT_STATUS, -                                val, (val 
>> & mask) == mask, -                                1000, 
>> CMD_PKT_STATUS_TIMEOUT_US); +       ret = 
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
>> val, (val & mask) == mask, + 
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); 
>>         if (ret) { 
>>                 dev_err(dsi->dev, "failed to write command 
>>                 FIFO\n"); return ret; 
>> @@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct 
>> dw_mipi_dsi *dsi, 
>>         const u8 *tx_buf = packet->payload; int len = 
>>         packet->payload_length, pld_data_bytes = sizeof(u32), 
>>         ret; __le32 word; 
>> -       u32 val; +       u32 val = 0; 
>> 
> 
> The same here, 'val' is used for the regmap_read_poll_timeout 
> and will be overwritten, no need to initialize. 
> 
>>         while (len) { 
>>                 if (len < pld_data_bytes) { 
>>                         word = 0; memcpy(&word, tx_buf, len); 
>> -                       dsi_write(dsi, DSI_GEN_PLD_DATA, 
>> le32_to_cpu(word)); + 
>> regmap_write(dsi->regs, DSI_GEN_PLD_DATA, + 
>> le32_to_cpu(word)); 
>>                         len = 0; 
>>                 } else { 
>>                         memcpy(&word, tx_buf, pld_data_bytes); 
>> -                       dsi_write(dsi, DSI_GEN_PLD_DATA, 
>> le32_to_cpu(word)); + 
>> regmap_write(dsi->regs, DSI_GEN_PLD_DATA, + 
>> le32_to_cpu(word)); 
>>                         tx_buf += pld_data_bytes; len -= 
>>                         pld_data_bytes; 
>>                 } 
>> 
>> -               ret = readl_poll_timeout(dsi->base + 
>> DSI_CMD_PKT_STATUS, - 
>> val, !(val & GEN_PLD_W_FULL), 1000, - 
>> CMD_PKT_STATUS_TIMEOUT_US); +               ret = 
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
>> val, !(val & GEN_PLD_W_FULL), + 
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); 
>>                 if (ret) { 
>>                         dev_err(dsi->dev, 
>>                                 "failed to get available write 
>>                                 payload FIFO\n"); 
>> @@ -438,12 +440,12 @@ static int dw_mipi_dsi_read(struct 
>> dw_mipi_dsi *dsi, 
>>  { 
>>         int i, j, ret, len = msg->rx_len; u8 *buf = 
>>         msg->rx_buf; 
>> -       u32 val; +       u32 val = 0; 
>> 
> 
> ditto 
> 
>>         /* Wait end of the read operation */ 
>> -       ret = readl_poll_timeout(dsi->base + 
>> DSI_CMD_PKT_STATUS, -                                val, !(val 
>> & GEN_RD_CMD_BUSY), -                                1000, 
>> CMD_PKT_STATUS_TIMEOUT_US); +       ret = 
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
>> val, !(val & GEN_RD_CMD_BUSY), + 
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); 
>>         if (ret) { 
>>                 dev_err(dsi->dev, "Timeout during read 
>>                 operation\n"); return ret; 
>> @@ -451,15 +453,15 @@ static int dw_mipi_dsi_read(struct 
>> dw_mipi_dsi *dsi, 
>> 
>>         for (i = 0; i < len; i += 4) { 
>>                 /* Read fifo must not be empty before all bytes 
>>                 are read */ 
>> -               ret = readl_poll_timeout(dsi->base + 
>> DSI_CMD_PKT_STATUS, - 
>> val, !(val & GEN_PLD_R_EMPTY), - 
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); +               ret = 
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
>> val, !(val & GEN_PLD_R_EMPTY), + 
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); 
>>                 if (ret) { 
>>                         dev_err(dsi->dev, "Read payload FIFO is 
>>                         empty\n"); return ret; 
>>                 } 
>> 
>> -               val = dsi_read(dsi, DSI_GEN_PLD_DATA); + 
>> regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val); 
>>                 for (j = 0; j < 4 && j + i < len; j++) 
>>                         buf[i + j] = val >> (8 * j); 
>>         } 
>> @@ -536,29 +538,29 @@ static void 
>> dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 
>>         } 
>>  #endif /* CONFIG_DEBUG_FS */ 
>> 
>> -       dsi_write(dsi, DSI_VID_MODE_CFG, val); + 
>> regmap_write(dsi->regs, DSI_VID_MODE_CFG, val); 
>>  } 
>> 
>>  static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, 
>>                                  unsigned long mode_flags) 
>>  { 
>> -       dsi_write(dsi, DSI_PWR_UP, RESET); + 
>> regmap_write(dsi->regs, DSI_PWR_UP, RESET); 
>> 
>>         if (mode_flags & MIPI_DSI_MODE_VIDEO) { 
>> -               dsi_write(dsi, DSI_MODE_CFG, 
>> ENABLE_VIDEO_MODE); +               regmap_write(dsi->regs, 
>> DSI_MODE_CFG, ENABLE_VIDEO_MODE); 
>>                 dw_mipi_dsi_video_mode_config(dsi); 
>> -               dsi_write(dsi, DSI_LPCLK_CTRL, 
>> PHY_TXREQUESTCLKHS); +               regmap_write(dsi->regs, 
>> DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); 
>>         } else { 
>> -               dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 
>> +               regmap_write(dsi->regs, DSI_MODE_CFG, 
>> ENABLE_CMD_MODE); 
>>         } 
>> 
>> -       dsi_write(dsi, DSI_PWR_UP, POWERUP); + 
>> regmap_write(dsi->regs, DSI_PWR_UP, POWERUP); 
>>  } 
>> 
>>  static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) { 
>> -       dsi_write(dsi, DSI_PWR_UP, RESET); - 
>> dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); + 
>> regmap_write(dsi->regs, DSI_PWR_UP, RESET); + 
>> regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ); 
>>  } 
>> 
>>  static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 
>> @@ -573,14 +575,14 @@ static void dw_mipi_dsi_init(struct 
>> dw_mipi_dsi *dsi) 
>>          */ 
>>         u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; 
>> 
>> -       dsi_write(dsi, DSI_PWR_UP, RESET); + 
>> regmap_write(dsi->regs, DSI_PWR_UP, RESET); 
>> 
>>         /* 
>>          * TODO dw drv improvements * timeout clock division 
>>          should be computed with the * high speed transmission 
>>          counter timeout and byte lane...  */ 
>> -       dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | + 
>> regmap_write(dsi->regs, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | 
>>                   TX_ESC_CLK_DIVISION(esc_clk_division)); 
>>  } 
>> 
>> @@ -609,22 +611,22 @@ static void dw_mipi_dsi_dpi_config(struct 
>> dw_mipi_dsi *dsi, 
>>         if (mode->flags & DRM_MODE_FLAG_NHSYNC) 
>>                 val |= HSYNC_ACTIVE_LOW; 
>> 
>> -       dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); - 
>> dsi_write(dsi, DSI_DPI_COLOR_CODING, color); - 
>> dsi_write(dsi, DSI_DPI_CFG_POL, val); + 
>> regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel)); 
>> +       regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color); + 
>> regmap_write(dsi->regs, DSI_DPI_CFG_POL, val); 
>>         /* 
>>          * TODO dw drv improvements * largest packet sizes 
>>          during hfp or during vsa/vpb/vfp * should be computed 
>>          according to byte lane, lane number and only * if 
>>          sending lp cmds in high speed is enable 
>>          (PHY_TXREQUESTCLKHS) */ 
>> -       dsi_write(dsi, DSI_DPI_LP_CMD_TIM, 
>> OUTVACT_LPCMD_TIME(4) +       regmap_write(dsi->regs, 
>> DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 
>>                   | INVACT_LPCMD_TIME(4)); 
>>  } 
>> 
>>  static void dw_mipi_dsi_packet_handler_config(struct 
>>  dw_mipi_dsi *dsi) { 
>> -       dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | 
>> BTA_EN); +       regmap_write(dsi->regs, DSI_PCKHDL_CFG, 
>> CRC_RX_EN | ECC_RX_EN | BTA_EN); 
>>  } 
>> 
>>  static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi 
>>  *dsi, 
>> @@ -638,7 +640,7 @@ static void 
>> dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 
>>          * non-burst video modes, see 
>>          dw_mipi_dsi_video_mode_config()...  */ 
>> 
>> -       dsi_write(dsi, DSI_VID_PKT_SIZE, + 
>> regmap_write(dsi->regs, DSI_VID_PKT_SIZE, 
>>                        dw_mipi_is_dual_mode(dsi) ? 
>>                                 VID_PKT_SIZE(mode->hdisplay / 
>>                                 2) : 
>>                                 VID_PKT_SIZE(mode->hdisplay)); 
>> @@ -651,14 +653,15 @@ static void 
>> dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 
>>          * compute high speed transmission counter timeout 
>>          according * to the timeout clock division 
>>          (TO_CLK_DIVISION) and byte lane...  */ 
>> -       dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | 
>> LPRX_TO_CNT(1000)); +       regmap_write(dsi->regs, 
>> DSI_TO_CNT_CFG, +                    HSTX_TO_CNT(1000) | 
>> LPRX_TO_CNT(1000)); 
>>         /* 
>>          * TODO dw drv improvements * the Bus-Turn-Around 
>>          Timeout Counter should be computed * according to byte 
>>          lane...  */ 
>> -       dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); - 
>> dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); + 
>> regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00); + 
>> regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE); 
>>  } 
>> 
>>  /* Get lane byte clock cycles. */ 
>> @@ -692,13 +695,13 @@ static void 
>> dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, 
>>          * computations below may be improved...  */ 
>>         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, 
>>         htotal); 
>> -       dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); + 
>> regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc); 
>> 
>>         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); 
>> -       dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); + 
>> regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc); 
>> 
>>         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); 
>> -       dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); + 
>> regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc); 
>>  } 
>> 
>>  static void dw_mipi_dsi_vertical_timing_config(struct 
>>  dw_mipi_dsi *dsi, 
>> @@ -711,10 +714,10 @@ static void 
>> dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, 
>>         vfp = mode->vsync_start - mode->vdisplay; vbp = 
>>         mode->vtotal - mode->vsync_end; 
>> 
>> -       dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); - 
>> dsi_write(dsi, DSI_VID_VSA_LINES, vsa); -       dsi_write(dsi, 
>> DSI_VID_VFP_LINES, vfp); -       dsi_write(dsi, 
>> DSI_VID_VBP_LINES, vbp); +       regmap_write(dsi->regs, 
>> DSI_VID_VACTIVE_LINES, vactive); + 
>> regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa); + 
>> regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp); + 
>> regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp); 
>>  } 
>> 
>>  static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi 
>>  *dsi) 
>> @@ -737,23 +740,25 @@ static void 
>> dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 
>>          * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see 
>>          CMD_MODE_ALL_LP) */ 
>> 
>> -       hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; + 
>> regmap_read(dsi->regs, DSI_VERSION, &hw_version); + 
>> hw_version &= VERSION; 
> 
> If I am not wrong, you already introduced a function to get the 
> hardware version and is stored in dsi->hw_version. Maybe you 
> could you use that variable and remove that code. 
>

Nice observation! There's a reason why I missed this change in the 
past:
in the next patch I remove the version check entirely from this 
function (yet another benefit of using regmap fields for layouts 
heh).

I will do this change because it makes the patch look a bit nicer 
:)

>>
>>         if (hw_version >= HWVER_131) {
>> -               dsi_write(dsi, DSI_PHY_TMR_CFG,
>> -                         PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
>> -                         PHY_LP2HS_TIME_V131(timing.data_lp2hs));
>> -               dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
>> +               regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
>> +                            PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
>> +                            PHY_LP2HS_TIME_V131(timing.data_lp2hs));
>> +               regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG,
>> +                            MAX_RD_TIME_V131(10000));
>>         } else {
>> -               dsi_write(dsi, DSI_PHY_TMR_CFG,
>> -                         PHY_HS2LP_TIME(timing.data_hs2lp) |
>> -                         PHY_LP2HS_TIME(timing.data_lp2hs) |
>> -                         MAX_RD_TIME(10000));
>> +               regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
>> +                            PHY_HS2LP_TIME(timing.data_hs2lp) |
>> +                            PHY_LP2HS_TIME(timing.data_lp2hs) |
>> +                            MAX_RD_TIME(10000));
>>         }
>>
>> -       dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
>> -                 PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
>> -                 PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
>> +       regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG,
>> +                    PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
>> +                    PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
>>  }
>>
>>  static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
>> @@ -763,46 +768,49 @@ static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
>>          * stop wait time should be the maximum between host dsi
>>          * and panel stop wait times
>>          */
>> -       dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
>> -                 N_LANES(dsi->lanes));
>> +       regmap_write(dsi->regs, DSI_PHY_IF_CFG,
>> +                    PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes));
>>  }
>>
>>  static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
>>  {
>>         /* Clear PHY state */
>> -       dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
>> -                 | PHY_RSTZ | PHY_SHUTDOWNZ);
>> -       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>> -       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
>> -       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>> +       regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
>> +                    | PHY_RSTZ | PHY_SHUTDOWNZ);
>> +       regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>> +       regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
>> +       regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>>  }
>>
>>  static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
>>  {
>> -       u32 val;
>> +       u32 val = 0;
>
> ditto
>
>>         int ret;
>>
>> -       dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
>> -                 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
>> +       regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
>> +                    PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
>>
>> -       ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
>> -                                val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
>> +       ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
>> +                                      val, val & PHY_LOCK,
>> +                                      1000, PHY_STATUS_TIMEOUT_US);
>>         if (ret)
>>                 DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
>>
>> -       ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>> -                                val, val & PHY_STOP_STATE_CLK_LANE, 1000,
>> -                                PHY_STATUS_TIMEOUT_US);
>> +       ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
>> +                                      val, val & PHY_STOP_STATE_CLK_LANE, 1000,
>> +                                      PHY_STATUS_TIMEOUT_US);
>>         if (ret)
>>                 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
>>  }
>>
>>  static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
>>  {
>> -       dsi_read(dsi, DSI_INT_ST0);
>> -       dsi_read(dsi, DSI_INT_ST1);
>> -       dsi_write(dsi, DSI_INT_MSK0, 0);
>> -       dsi_write(dsi, DSI_INT_MSK1, 0);
>> +       u32 val;
>> +
>> +       regmap_read(dsi->regs, DSI_INT_ST0, &val);
>> +       regmap_read(dsi->regs, DSI_INT_ST1, &val);
>> +       regmap_write(dsi->regs, DSI_INT_MSK0, 0);
>> +       regmap_write(dsi->regs, DSI_INT_MSK1, 0);
>>  }
>>
>>  static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
>> @@ -989,6 +997,14 @@ static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
>>
>>  #endif /* CONFIG_DEBUG_FS */
>>
>> +static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi *dsi)
>> +{
>> +       regmap_read(dsi->regs, DSI_VERSION, &dsi->hw_version);
>> +       dsi->hw_version &= VERSION;
>> +       if (!dsi->hw_version)
>> +               dev_err(dsi->dev, "Failed to read DSI hw version register\n");
>
> Is this an error that should be ignored? If you can't get the HW
> version, probably, there is something wrong with your hardware so,
> don't you need to return an error?
>
>
>> +}
>> +
>>  static struct dw_mipi_dsi *
>>  __dw_mipi_dsi_probe(struct platform_device *pdev,
>>                     const struct dw_mipi_dsi_plat_data *plat_data)
>> @@ -1020,6 +1036,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>>                 dsi->base = plat_data->base;
>>         }
>>
>> +       dsi->regs = devm_regmap_init_mmio(dev, dsi->base,
>> +                                         &dw_mipi_dsi_regmap_cfg);
>> +       if (IS_ERR(dsi->regs)) {
>> +               ret = PTR_ERR(dsi->regs);
>> +               DRM_ERROR("Failed to create DW MIPI DSI regmap: %d\n", ret);
>> +               return ERR_PTR(ret);
>> +       }
>> +
>>         dsi->pclk = devm_clk_get(dev, "pclk");
>>         if (IS_ERR(dsi->pclk)) {
>>                 ret = PTR_ERR(dsi->pclk);
>> @@ -1055,6 +1079,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>>                 clk_disable_unprepare(dsi->pclk);
>>         }
>>
>> +       dw_mipi_dsi_get_hw_version(dsi);
>> +
>>         dw_mipi_dsi_debugfs_init(dsi);
>>         pm_runtime_enable(dev);
>>
>> --
>> 2.26.0
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH v6 1/8] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

[Adrian Ratiu]

On Wed, 15 Apr 2020, Enric Balletbo Serra <eballetbo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 
wrote:
> Hi Adrian, 
> 
> Some few comments/nits below, 
> 
> Missatge de Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> del dia 
> dt., 14 d’abr. 2020 a les 17:19: 
>> 
>> In order to support multiple versions of the Synopsis MIPI DSI 
>> host controller, which have different register layouts but 
>> almost identical HW protocols, we add a regmap infrastructure 
>> which can abstract away register accesses for platform drivers 
>> using the bridge. 
>> 
>> The controller HW revision is detected during bridge probe 
>> which will be used in future commits to load the relevant 
>> register layout which the bridge will use transparently to the 
>> platform drivers. 
>> 
>> Suggested-by: Ezequiel Garcia <ezequiel-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> 
>> Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Tested-by: 
>> Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> Signed-off-by: 
>> Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> --- New in v5.  --- 
>>  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208 
>>  ++++++++++-------- 1 file changed, 117 insertions(+), 91 
>>  deletions(-) 
>> 
>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 
>> 5ef0f154aa7b..6d9e2f21c9cc 100644 --- 
>> a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ 
>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -15,6 +15,7 
>> @@ 
>>  #include <linux/module.h> #include <linux/of_device.h> 
>>  #include <linux/pm_runtime.h> 
>> +#include <linux/regmap.h> 
> 
> Should Kconfig select REGMAP for this driver? 
> 
>>  #include <linux/reset.h> 
>> 
>>  #include <video/mipi_display.h> 
>> @@ -227,6 +228,7 @@ struct dw_mipi_dsi { 
>>         struct drm_bridge *panel_bridge; struct device *dev; 
>>         void __iomem *base; 
>> +       struct regmap *regs; 
>> 
>>         struct clk *pclk; 
>> 
>> @@ -235,6 +237,7 @@ struct dw_mipi_dsi { 
>>         u32 lanes; u32 format; unsigned long mode_flags; 
>> +       u32 hw_version; 
>> 
>>  #ifdef CONFIG_DEBUG_FS 
>>         struct dentry *debugfs; 
>> @@ -249,6 +252,13 @@ struct dw_mipi_dsi { 
>>         const struct dw_mipi_dsi_plat_data *plat_data; 
>>  }; 
>> 
>> +static const struct regmap_config dw_mipi_dsi_regmap_cfg = { + 
>> .reg_bits = 32, +       .val_bits = 32, +       .reg_stride = 
>> 4, +       .name = "dw-mipi-dsi", +}; + 
>>  /* 
>>   * Check if either a link to a master or slave is present */ 
>> @@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi 
>> *bridge_to_dsi(struct drm_bridge *bridge) 
>>         return container_of(bridge, struct dw_mipi_dsi, 
>>         bridge); 
>>  } 
>> 
>> -static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, 
>> u32 val) -{ -       writel(val, dsi->base + reg); -} - -static 
>> inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) -{ - 
>> return readl(dsi->base + reg); -} - 
>>  static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 
>>                                    struct mipi_dsi_device 
>>                                    *device) 
>>  { 
>> @@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct 
>> dw_mipi_dsi *dsi, 
>>         if (lpm) 
>>                 val |= CMD_MODE_ALL_LP; 
>> 
>> -       dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : 
>> PHY_TXREQUESTCLKHS); -       dsi_write(dsi, DSI_CMD_MODE_CFG, 
>> val); +       regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : 
>> PHY_TXREQUESTCLKHS); +       regmap_write(dsi->regs, 
>> DSI_CMD_MODE_CFG, val); 
>>  } 
>> 
>>  static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi 
>>  *dsi, u32 hdr_val) { 
>>         int ret; 
>> -       u32 val, mask; +       u32 val = 0, mask; 
>> 
> 
> I think that this change is not needed, `val` is an input 
> variable that will be overwritten inside the 
> regmap_read_poll_timeout.  Initialize here is not needed. 
> 
>> -       ret = readl_poll_timeout(dsi->base + 
>> DSI_CMD_PKT_STATUS, -                                val, !(val 
>> & GEN_CMD_FULL), 1000, - 
>> CMD_PKT_STATUS_TIMEOUT_US); +       ret = 
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
>> val, !(val & GEN_CMD_FULL), 1000, + 
>> CMD_PKT_STATUS_TIMEOUT_US); 
>>         if (ret) { 
>>                 dev_err(dsi->dev, "failed to get available 
>>                 command FIFO\n"); return ret; 
>>         } 
>> 
>> -       dsi_write(dsi, DSI_GEN_HDR, hdr_val); + 
>> regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val); 
>> 
>>         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 
>> -       ret = readl_poll_timeout(dsi->base + 
>> DSI_CMD_PKT_STATUS, -                                val, (val 
>> & mask) == mask, -                                1000, 
>> CMD_PKT_STATUS_TIMEOUT_US); +       ret = 
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
>> val, (val & mask) == mask, + 
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); 
>>         if (ret) { 
>>                 dev_err(dsi->dev, "failed to write command 
>>                 FIFO\n"); return ret; 
>> @@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct 
>> dw_mipi_dsi *dsi, 
>>         const u8 *tx_buf = packet->payload; int len = 
>>         packet->payload_length, pld_data_bytes = sizeof(u32), 
>>         ret; __le32 word; 
>> -       u32 val; +       u32 val = 0; 
>> 
> 
> The same here, 'val' is used for the regmap_read_poll_timeout 
> and will be overwritten, no need to initialize. 
> 
>>         while (len) { 
>>                 if (len < pld_data_bytes) { 
>>                         word = 0; memcpy(&word, tx_buf, len); 
>> -                       dsi_write(dsi, DSI_GEN_PLD_DATA, 
>> le32_to_cpu(word)); + 
>> regmap_write(dsi->regs, DSI_GEN_PLD_DATA, + 
>> le32_to_cpu(word)); 
>>                         len = 0; 
>>                 } else { 
>>                         memcpy(&word, tx_buf, pld_data_bytes); 
>> -                       dsi_write(dsi, DSI_GEN_PLD_DATA, 
>> le32_to_cpu(word)); + 
>> regmap_write(dsi->regs, DSI_GEN_PLD_DATA, + 
>> le32_to_cpu(word)); 
>>                         tx_buf += pld_data_bytes; len -= 
>>                         pld_data_bytes; 
>>                 } 
>> 
>> -               ret = readl_poll_timeout(dsi->base + 
>> DSI_CMD_PKT_STATUS, - 
>> val, !(val & GEN_PLD_W_FULL), 1000, - 
>> CMD_PKT_STATUS_TIMEOUT_US); +               ret = 
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
>> val, !(val & GEN_PLD_W_FULL), + 
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); 
>>                 if (ret) { 
>>                         dev_err(dsi->dev, 
>>                                 "failed to get available write 
>>                                 payload FIFO\n"); 
>> @@ -438,12 +440,12 @@ static int dw_mipi_dsi_read(struct 
>> dw_mipi_dsi *dsi, 
>>  { 
>>         int i, j, ret, len = msg->rx_len; u8 *buf = 
>>         msg->rx_buf; 
>> -       u32 val; +       u32 val = 0; 
>> 
> 
> ditto 
> 
>>         /* Wait end of the read operation */ 
>> -       ret = readl_poll_timeout(dsi->base + 
>> DSI_CMD_PKT_STATUS, -                                val, !(val 
>> & GEN_RD_CMD_BUSY), -                                1000, 
>> CMD_PKT_STATUS_TIMEOUT_US); +       ret = 
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
>> val, !(val & GEN_RD_CMD_BUSY), + 
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); 
>>         if (ret) { 
>>                 dev_err(dsi->dev, "Timeout during read 
>>                 operation\n"); return ret; 
>> @@ -451,15 +453,15 @@ static int dw_mipi_dsi_read(struct 
>> dw_mipi_dsi *dsi, 
>> 
>>         for (i = 0; i < len; i += 4) { 
>>                 /* Read fifo must not be empty before all bytes 
>>                 are read */ 
>> -               ret = readl_poll_timeout(dsi->base + 
>> DSI_CMD_PKT_STATUS, - 
>> val, !(val & GEN_PLD_R_EMPTY), - 
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); +               ret = 
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
>> val, !(val & GEN_PLD_R_EMPTY), + 
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); 
>>                 if (ret) { 
>>                         dev_err(dsi->dev, "Read payload FIFO is 
>>                         empty\n"); return ret; 
>>                 } 
>> 
>> -               val = dsi_read(dsi, DSI_GEN_PLD_DATA); + 
>> regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val); 
>>                 for (j = 0; j < 4 && j + i < len; j++) 
>>                         buf[i + j] = val >> (8 * j); 
>>         } 
>> @@ -536,29 +538,29 @@ static void 
>> dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 
>>         } 
>>  #endif /* CONFIG_DEBUG_FS */ 
>> 
>> -       dsi_write(dsi, DSI_VID_MODE_CFG, val); + 
>> regmap_write(dsi->regs, DSI_VID_MODE_CFG, val); 
>>  } 
>> 
>>  static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, 
>>                                  unsigned long mode_flags) 
>>  { 
>> -       dsi_write(dsi, DSI_PWR_UP, RESET); + 
>> regmap_write(dsi->regs, DSI_PWR_UP, RESET); 
>> 
>>         if (mode_flags & MIPI_DSI_MODE_VIDEO) { 
>> -               dsi_write(dsi, DSI_MODE_CFG, 
>> ENABLE_VIDEO_MODE); +               regmap_write(dsi->regs, 
>> DSI_MODE_CFG, ENABLE_VIDEO_MODE); 
>>                 dw_mipi_dsi_video_mode_config(dsi); 
>> -               dsi_write(dsi, DSI_LPCLK_CTRL, 
>> PHY_TXREQUESTCLKHS); +               regmap_write(dsi->regs, 
>> DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); 
>>         } else { 
>> -               dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 
>> +               regmap_write(dsi->regs, DSI_MODE_CFG, 
>> ENABLE_CMD_MODE); 
>>         } 
>> 
>> -       dsi_write(dsi, DSI_PWR_UP, POWERUP); + 
>> regmap_write(dsi->regs, DSI_PWR_UP, POWERUP); 
>>  } 
>> 
>>  static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) { 
>> -       dsi_write(dsi, DSI_PWR_UP, RESET); - 
>> dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); + 
>> regmap_write(dsi->regs, DSI_PWR_UP, RESET); + 
>> regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ); 
>>  } 
>> 
>>  static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 
>> @@ -573,14 +575,14 @@ static void dw_mipi_dsi_init(struct 
>> dw_mipi_dsi *dsi) 
>>          */ 
>>         u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; 
>> 
>> -       dsi_write(dsi, DSI_PWR_UP, RESET); + 
>> regmap_write(dsi->regs, DSI_PWR_UP, RESET); 
>> 
>>         /* 
>>          * TODO dw drv improvements * timeout clock division 
>>          should be computed with the * high speed transmission 
>>          counter timeout and byte lane...  */ 
>> -       dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | + 
>> regmap_write(dsi->regs, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | 
>>                   TX_ESC_CLK_DIVISION(esc_clk_division)); 
>>  } 
>> 
>> @@ -609,22 +611,22 @@ static void dw_mipi_dsi_dpi_config(struct 
>> dw_mipi_dsi *dsi, 
>>         if (mode->flags & DRM_MODE_FLAG_NHSYNC) 
>>                 val |= HSYNC_ACTIVE_LOW; 
>> 
>> -       dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); - 
>> dsi_write(dsi, DSI_DPI_COLOR_CODING, color); - 
>> dsi_write(dsi, DSI_DPI_CFG_POL, val); + 
>> regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel)); 
>> +       regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color); + 
>> regmap_write(dsi->regs, DSI_DPI_CFG_POL, val); 
>>         /* 
>>          * TODO dw drv improvements * largest packet sizes 
>>          during hfp or during vsa/vpb/vfp * should be computed 
>>          according to byte lane, lane number and only * if 
>>          sending lp cmds in high speed is enable 
>>          (PHY_TXREQUESTCLKHS) */ 
>> -       dsi_write(dsi, DSI_DPI_LP_CMD_TIM, 
>> OUTVACT_LPCMD_TIME(4) +       regmap_write(dsi->regs, 
>> DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 
>>                   | INVACT_LPCMD_TIME(4)); 
>>  } 
>> 
>>  static void dw_mipi_dsi_packet_handler_config(struct 
>>  dw_mipi_dsi *dsi) { 
>> -       dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | 
>> BTA_EN); +       regmap_write(dsi->regs, DSI_PCKHDL_CFG, 
>> CRC_RX_EN | ECC_RX_EN | BTA_EN); 
>>  } 
>> 
>>  static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi 
>>  *dsi, 
>> @@ -638,7 +640,7 @@ static void 
>> dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 
>>          * non-burst video modes, see 
>>          dw_mipi_dsi_video_mode_config()...  */ 
>> 
>> -       dsi_write(dsi, DSI_VID_PKT_SIZE, + 
>> regmap_write(dsi->regs, DSI_VID_PKT_SIZE, 
>>                        dw_mipi_is_dual_mode(dsi) ? 
>>                                 VID_PKT_SIZE(mode->hdisplay / 
>>                                 2) : 
>>                                 VID_PKT_SIZE(mode->hdisplay)); 
>> @@ -651,14 +653,15 @@ static void 
>> dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 
>>          * compute high speed transmission counter timeout 
>>          according * to the timeout clock division 
>>          (TO_CLK_DIVISION) and byte lane...  */ 
>> -       dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | 
>> LPRX_TO_CNT(1000)); +       regmap_write(dsi->regs, 
>> DSI_TO_CNT_CFG, +                    HSTX_TO_CNT(1000) | 
>> LPRX_TO_CNT(1000)); 
>>         /* 
>>          * TODO dw drv improvements * the Bus-Turn-Around 
>>          Timeout Counter should be computed * according to byte 
>>          lane...  */ 
>> -       dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); - 
>> dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); + 
>> regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00); + 
>> regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE); 
>>  } 
>> 
>>  /* Get lane byte clock cycles. */ 
>> @@ -692,13 +695,13 @@ static void 
>> dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, 
>>          * computations below may be improved...  */ 
>>         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, 
>>         htotal); 
>> -       dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); + 
>> regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc); 
>> 
>>         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); 
>> -       dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); + 
>> regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc); 
>> 
>>         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); 
>> -       dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); + 
>> regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc); 
>>  } 
>> 
>>  static void dw_mipi_dsi_vertical_timing_config(struct 
>>  dw_mipi_dsi *dsi, 
>> @@ -711,10 +714,10 @@ static void 
>> dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, 
>>         vfp = mode->vsync_start - mode->vdisplay; vbp = 
>>         mode->vtotal - mode->vsync_end; 
>> 
>> -       dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); - 
>> dsi_write(dsi, DSI_VID_VSA_LINES, vsa); -       dsi_write(dsi, 
>> DSI_VID_VFP_LINES, vfp); -       dsi_write(dsi, 
>> DSI_VID_VBP_LINES, vbp); +       regmap_write(dsi->regs, 
>> DSI_VID_VACTIVE_LINES, vactive); + 
>> regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa); + 
>> regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp); + 
>> regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp); 
>>  } 
>> 
>>  static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi 
>>  *dsi) 
>> @@ -737,23 +740,25 @@ static void 
>> dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 
>>          * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see 
>>          CMD_MODE_ALL_LP) */ 
>> 
>> -       hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; + 
>> regmap_read(dsi->regs, DSI_VERSION, &hw_version); + 
>> hw_version &= VERSION; 
> 
> If I am not wrong, you already introduced a function to get the 
> hardware version and is stored in dsi->hw_version. Maybe you 
> could you use that variable and remove that code. 
> 
>> 
>>         if (hw_version >= HWVER_131) { 
>> -               dsi_write(dsi, DSI_PHY_TMR_CFG, - 
>> PHY_HS2LP_TIME_V131(timing.data_hs2lp) | - 
>> PHY_LP2HS_TIME_V131(timing.data_lp2hs)); - 
>> dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); + 
>> regmap_write(dsi->regs, DSI_PHY_TMR_CFG, + 
>> PHY_HS2LP_TIME_V131(timing.data_hs2lp) | + 
>> PHY_LP2HS_TIME_V131(timing.data_lp2hs)); + 
>> regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG, + 
>> MAX_RD_TIME_V131(10000)); 
>>         } else { 
>> -               dsi_write(dsi, DSI_PHY_TMR_CFG, - 
>> PHY_HS2LP_TIME(timing.data_hs2lp) | - 
>> PHY_LP2HS_TIME(timing.data_lp2hs) | - 
>> MAX_RD_TIME(10000)); +               regmap_write(dsi->regs, 
>> DSI_PHY_TMR_CFG, + 
>> PHY_HS2LP_TIME(timing.data_hs2lp) | + 
>> PHY_LP2HS_TIME(timing.data_lp2hs) | + 
>> MAX_RD_TIME(10000)); 
>>         } 
>> 
>> -       dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, - 
>> PHY_CLKHS2LP_TIME(timing.clk_hs2lp) | - 
>> PHY_CLKLP2HS_TIME(timing.clk_lp2hs)); + 
>> regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG, + 
>> PHY_CLKHS2LP_TIME(timing.clk_hs2lp) | + 
>> PHY_CLKLP2HS_TIME(timing.clk_lp2hs)); 
>>  } 
>> 
>>  static void dw_mipi_dsi_dphy_interface_config(struct 
>>  dw_mipi_dsi *dsi) 
>> @@ -763,46 +768,49 @@ static void 
>> dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 
>>          * stop wait time should be the maximum between host 
>>          dsi * and panel stop wait times */ 
>> -       dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) 
>> | -                 N_LANES(dsi->lanes)); + 
>> regmap_write(dsi->regs, DSI_PHY_IF_CFG, + 
>> PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes)); 
>>  } 
>> 
>>  static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) { 
>>         /* Clear PHY state */ 
>> -       dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | 
>> PHY_DISABLECLK -                 | PHY_RSTZ | PHY_SHUTDOWNZ); - 
>> dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); - 
>> dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); - 
>> dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); + 
>> regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL | 
>> PHY_DISABLECLK +                    | PHY_RSTZ | 
>> PHY_SHUTDOWNZ); +       regmap_write(dsi->regs, 
>> DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); + 
>> regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR); + 
>> regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 
>>  } 
>> 
>>  static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) { 
>> -       u32 val; +       u32 val = 0; 
> 
> ditto 
> 
>>         int ret; 
>> 
>> -       dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | 
>> PHY_ENABLECLK | -                 PHY_UNRSTZ | 
>> PHY_UNSHUTDOWNZ); +       regmap_write(dsi->regs, DSI_PHY_RSTZ, 
>> PHY_ENFORCEPLL | PHY_ENABLECLK | + 
>> PHY_UNRSTZ | PHY_UNSHUTDOWNZ); 
>> 
>> -       ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 
>> val, -                                val & PHY_LOCK, 1000, 
>> PHY_STATUS_TIMEOUT_US); +       ret = 
>> regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS, + 
>> val, val & PHY_LOCK, + 
>> 1000, PHY_STATUS_TIMEOUT_US); 
>>         if (ret) 
>>                 DRM_DEBUG_DRIVER("failed to wait phy lock 
>>                 state\n"); 
>> 
>> -       ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, - 
>> val, val & PHY_STOP_STATE_CLK_LANE, 1000, - 
>> PHY_STATUS_TIMEOUT_US); +       ret = 
>> regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS, + 
>> val, val & PHY_STOP_STATE_CLK_LANE, 1000, + 
>> PHY_STATUS_TIMEOUT_US); 
>>         if (ret) 
>>                 DRM_DEBUG_DRIVER("failed to wait phy clk lane 
>>                 stop state\n"); 
>>  } 
>> 
>>  static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) { 
>> -       dsi_read(dsi, DSI_INT_ST0); -       dsi_read(dsi, 
>> DSI_INT_ST1); -       dsi_write(dsi, DSI_INT_MSK0, 0); - 
>> dsi_write(dsi, DSI_INT_MSK1, 0); +       u32 val; + + 
>> regmap_read(dsi->regs, DSI_INT_ST0, &val); + 
>> regmap_read(dsi->regs, DSI_INT_ST1, &val); + 
>> regmap_write(dsi->regs, DSI_INT_MSK0, 0); + 
>> regmap_write(dsi->regs, DSI_INT_MSK1, 0); 
>>  } 
>> 
>>  static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge 
>>  *bridge) 
>> @@ -989,6 +997,14 @@ static void 
>> dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { } 
>> 
>>  #endif /* CONFIG_DEBUG_FS */ 
>> 
>> +static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi 
>> *dsi) +{ +       regmap_read(dsi->regs, DSI_VERSION, 
>> &dsi->hw_version); +       dsi->hw_version &= VERSION; + 
>> if (!dsi->hw_version) +               dev_err(dsi->dev, "Failed 
>> to read DSI hw version register\n"); 
> 
> Is this an error that should be ignored? If you can't get the HW 
> version, probably, there is something wrong with your hardware 
> so, don't you need to return an error? 
> 

After thinking a bit more about it, that error should be a 
warning.

I added it because in some cases (for eg. if the peripheral clock 
is disabled) the reads can return 0 which is obviously an invalid 
version and the bridge will error in the next step when not 
finding a layout.

So I'll make this a warning in v7 and explicitely mention that 
reads version == 0 can be caused by a disabled pclk.

>> +}
>> +
>>  static struct dw_mipi_dsi *
>>  __dw_mipi_dsi_probe(struct platform_device *pdev,
>>                     const struct dw_mipi_dsi_plat_data *plat_data)
>> @@ -1020,6 +1036,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>>                 dsi->base = plat_data->base;
>>         }
>>
>> +       dsi->regs = devm_regmap_init_mmio(dev, dsi->base,
>> +                                         &dw_mipi_dsi_regmap_cfg);
>> +       if (IS_ERR(dsi->regs)) {
>> +               ret = PTR_ERR(dsi->regs);
>> +               DRM_ERROR("Failed to create DW MIPI DSI regmap: %d\n", ret);
>> +               return ERR_PTR(ret);
>> +       }
>> +
>>         dsi->pclk = devm_clk_get(dev, "pclk");
>>         if (IS_ERR(dsi->pclk)) {
>>                 ret = PTR_ERR(dsi->pclk);
>> @@ -1055,6 +1079,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>>                 clk_disable_unprepare(dsi->pclk);
>>         }
>>
>> +       dw_mipi_dsi_get_hw_version(dsi);
>> +
>>         dw_mipi_dsi_debugfs_init(dsi);
>>         pm_runtime_enable(dev);
>>
>> --
>> 2.26.0
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH v6 1/8] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

[Enric Balletbo Serra]

Hi Adrian,

[snip]

> >>
> >> +static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi
> >> *dsi) +{ +       regmap_read(dsi->regs, DSI_VERSION,
> >> &dsi->hw_version); +       dsi->hw_version &= VERSION; +
> >> if (!dsi->hw_version) +               dev_err(dsi->dev, "Failed
> >> to read DSI hw version register\n");
> >
> > Is this an error that should be ignored? If you can't get the HW
> > version, probably, there is something wrong with your hardware
> > so, don't you need to return an error?
> >
>
> After thinking a bit more about it, that error should be a
> warning.
>
> I added it because in some cases (for eg. if the peripheral clock
> is disabled) the reads can return 0 which is obviously an invalid
> version and the bridge will error in the next step when not
> finding a layout.
>

If you'll error anyway, why wait? IIUC at this point the clock *must*
be enabled, and if not, something is wrong with the driver, I don't
see any advantage on delay the error. do you have a use case where
this is called and peripheral clock disabled?

> So I'll make this a warning in v7 and explicitely mention that
> reads version == 0 can be caused by a disabled pclk.
>

-- Enric

Re: [PATCH v6 1/8] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

[Adrian Ratiu]

On Thu, 16 Apr 2020, Enric Balletbo Serra <eballetbo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 
wrote:
> Hi Adrian, 
> 
> [snip] 
> 
>> >> 
>> >> +static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi 
>> >> *dsi) +{ +       regmap_read(dsi->regs, DSI_VERSION, 
>> >> &dsi->hw_version); +       dsi->hw_version &= VERSION; + if 
>> >> (!dsi->hw_version) +               dev_err(dsi->dev, "Failed 
>> >> to read DSI hw version register\n"); 
>> > 
>> > Is this an error that should be ignored? If you can't get the 
>> > HW version, probably, there is something wrong with your 
>> > hardware so, don't you need to return an error? 
>> > 
>> 
>> After thinking a bit more about it, that error should be a 
>> warning. 
>> 
>> I added it because in some cases (for eg. if the peripheral 
>> clock is disabled) the reads can return 0 which is obviously an 
>> invalid version and the bridge will error in the next step when 
>> not finding a layout. 
>> 
> 
> If you'll error anyway, why wait? IIUC at this point the clock 
> *must* be enabled, and if not, something is wrong with the 
> driver, I don't see any advantage on delay the error. do you 
> have a use case where this is called and peripheral clock 
> disabled? 

There should be no real use-case (maybe malfunctioning HW), and we 
could error out here to catch driver bugs ASAP, so I'll go this 
route then :)

Thank you, much appreciated!

>
>> So I'll make this a warning in v7 and explicitely mention that
>> reads version == 0 can be caused by a disabled pclk.
>>
>
> -- Enric
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v6 2/8] drm: bridge: dw_mipi_dsi: abstract register access using reg_fields

[Adrian Ratiu]

Register existence, address/offsets, field layouts, reserved bits and
so on differ between MIPI-DSI versions and between SoC vendor boards.
Despite these differences the hw IP and protocols are mostly the same
so the generic bridge can be made to compensate these differences.

The current Rockchip and STM drivers hardcoded a lot of their common
definitions in the bridge code because they're based on DSI v1.30 and
1.31 which are relatively close, but in order to support older/future
versions with more diverging layouts like the v1.01 present on imx6,
we abstract some of the register accesses via the regmap field APIs.

The bridge detects the DSI core version and initializes the required
regmap register layout. Other DSI versions / register layouts can
easily be added in the future by only changing the bridge code.

The platform drivers don't require any changes, DSI register layout
versioning will be handled transparently by the bridge, but if in
the future the regmap or layouts needs to be exposed to the drivres,
it could easily be done via plat_data or a new API in dw_mipi_dsi.h.

Suggested-by: Boris Brezillon <boris.brezillon-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Reviewed-by: Emil Velikov <emil.velikov-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Signed-off-by: Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
Changes since v5:
  - Fix CONFIG_DEBUG_FS build (Adrian)
  - Fix DRM_MODE_FLAG_* test negation (Adrian)
  - Fixed cfg_phy_status range from [0,0] to [0,2]
  - Replace do {} while(0) with GCC extension ({}) (Andrzej)
  - Fixed payload no-op writes on STM devices (Adrian & Arnaud)

Changes since v4:
  - Move regmap infrastructure logic to a separate commit (Ezequiel)
  - Consolidate field infrastructure in this commit (Ezequiel)
  - Move the dsi v1.01 layout logic to a separate commit (Ezequiel)

Changes since v2:
  - Added const declarations to dw_mipi_dsi structs (Emil)
  - Fixed commit tags (Emil)

Changes since v1:
  - Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after calling
  the bridge probe (Emil).
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 503 ++++++++++++------
 1 file changed, 347 insertions(+), 156 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 6d9e2f21c9cc..f72643e25669 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -31,6 +31,7 @@
 #include <drm/drm_probe_helper.h>
 
 #define HWVER_131			0x31333100	/* IP version 1.31 */
+#define HWVER_130			0x31333000	/* IP version 1.30 */
 
 #define DSI_VERSION			0x00
 #define VERSION				GENMASK(31, 8)
@@ -47,7 +48,6 @@
 #define DPI_VCID(vcid)			((vcid) & 0x3)
 
 #define DSI_DPI_COLOR_CODING		0x10
-#define LOOSELY18_EN			BIT(8)
 #define DPI_COLOR_CODING_16BIT_1	0x0
 #define DPI_COLOR_CODING_16BIT_2	0x1
 #define DPI_COLOR_CODING_16BIT_3	0x2
@@ -56,11 +56,6 @@
 #define DPI_COLOR_CODING_24BIT		0x5
 
 #define DSI_DPI_CFG_POL			0x14
-#define COLORM_ACTIVE_LOW		BIT(4)
-#define SHUTD_ACTIVE_LOW		BIT(3)
-#define HSYNC_ACTIVE_LOW		BIT(2)
-#define VSYNC_ACTIVE_LOW		BIT(1)
-#define DATAEN_ACTIVE_LOW		BIT(0)
 
 #define DSI_DPI_LP_CMD_TIM		0x18
 #define OUTVACT_LPCMD_TIME(p)		(((p) & 0xff) << 16)
@@ -81,27 +76,19 @@
 #define DSI_GEN_VCID			0x30
 
 #define DSI_MODE_CFG			0x34
-#define ENABLE_VIDEO_MODE		0
-#define ENABLE_CMD_MODE			BIT(0)
 
 #define DSI_VID_MODE_CFG		0x38
-#define ENABLE_LOW_POWER		(0x3f << 8)
-#define ENABLE_LOW_POWER_MASK		(0x3f << 8)
+#define ENABLE_LOW_POWER		0x3f
+
 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES	0x0
 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS	0x1
 #define VID_MODE_TYPE_BURST			0x2
-#define VID_MODE_TYPE_MASK			0x3
-#define VID_MODE_VPG_ENABLE		BIT(16)
-#define VID_MODE_VPG_HORIZONTAL		BIT(24)
 
 #define DSI_VID_PKT_SIZE		0x3c
-#define VID_PKT_SIZE(p)			((p) & 0x3fff)
 
 #define DSI_VID_NUM_CHUNKS		0x40
-#define VID_NUM_CHUNKS(c)		((c) & 0x1fff)
 
 #define DSI_VID_NULL_SIZE		0x44
-#define VID_NULL_SIZE(b)		((b) & 0x1fff)
 
 #define DSI_VID_HSA_TIME		0x48
 #define DSI_VID_HBP_TIME		0x4c
@@ -125,7 +112,6 @@
 #define GEN_SW_2P_TX_LP			BIT(10)
 #define GEN_SW_1P_TX_LP			BIT(9)
 #define GEN_SW_0P_TX_LP			BIT(8)
-#define ACK_RQST_EN			BIT(1)
 #define TEAR_FX_EN			BIT(0)
 
 #define CMD_MODE_ALL_LP			(MAX_RD_PKT_SIZE_LP | \
@@ -154,8 +140,6 @@
 #define GEN_CMD_EMPTY			BIT(0)
 
 #define DSI_TO_CNT_CFG			0x78
-#define HSTX_TO_CNT(p)			(((p) & 0xffff) << 16)
-#define LPRX_TO_CNT(p)			((p) & 0xffff)
 
 #define DSI_HS_RD_TO_CNT		0x7c
 #define DSI_LP_RD_TO_CNT		0x80
@@ -164,52 +148,17 @@
 #define DSI_BTA_TO_CNT			0x8c
 
 #define DSI_LPCLK_CTRL			0x94
-#define AUTO_CLKLANE_CTRL		BIT(1)
-#define PHY_TXREQUESTCLKHS		BIT(0)
-
 #define DSI_PHY_TMR_LPCLK_CFG		0x98
-#define PHY_CLKHS2LP_TIME(lbcc)		(((lbcc) & 0x3ff) << 16)
-#define PHY_CLKLP2HS_TIME(lbcc)		((lbcc) & 0x3ff)
-
 #define DSI_PHY_TMR_CFG			0x9c
-#define PHY_HS2LP_TIME(lbcc)		(((lbcc) & 0xff) << 24)
-#define PHY_LP2HS_TIME(lbcc)		(((lbcc) & 0xff) << 16)
-#define MAX_RD_TIME(lbcc)		((lbcc) & 0x7fff)
-#define PHY_HS2LP_TIME_V131(lbcc)	(((lbcc) & 0x3ff) << 16)
-#define PHY_LP2HS_TIME_V131(lbcc)	((lbcc) & 0x3ff)
-
 #define DSI_PHY_RSTZ			0xa0
-#define PHY_DISFORCEPLL			0
-#define PHY_ENFORCEPLL			BIT(3)
-#define PHY_DISABLECLK			0
-#define PHY_ENABLECLK			BIT(2)
-#define PHY_RSTZ			0
-#define PHY_UNRSTZ			BIT(1)
-#define PHY_SHUTDOWNZ			0
-#define PHY_UNSHUTDOWNZ			BIT(0)
-
 #define DSI_PHY_IF_CFG			0xa4
-#define PHY_STOP_WAIT_TIME(cycle)	(((cycle) & 0xff) << 8)
-#define N_LANES(n)			(((n) - 1) & 0x3)
-
-#define DSI_PHY_ULPS_CTRL		0xa8
-#define DSI_PHY_TX_TRIGGERS		0xac
 
 #define DSI_PHY_STATUS			0xb0
 #define PHY_STOP_STATE_CLK_LANE		BIT(2)
 #define PHY_LOCK			BIT(0)
 
 #define DSI_PHY_TST_CTRL0		0xb4
-#define PHY_TESTCLK			BIT(1)
-#define PHY_UNTESTCLK			0
-#define PHY_TESTCLR			BIT(0)
-#define PHY_UNTESTCLR			0
-
 #define DSI_PHY_TST_CTRL1		0xb8
-#define PHY_TESTEN			BIT(16)
-#define PHY_UNTESTEN			0
-#define PHY_TESTDOUT(n)			(((n) & 0xff) << 8)
-#define PHY_TESTDIN(n)			((n) & 0xff)
 
 #define DSI_INT_ST0			0xbc
 #define DSI_INT_ST1			0xc0
@@ -217,7 +166,6 @@
 #define DSI_INT_MSK1			0xc8
 
 #define DSI_PHY_TMR_RD_CFG		0xf4
-#define MAX_RD_TIME_V131(lbcc)		((lbcc) & 0x7fff)
 
 #define PHY_STATUS_TIMEOUT_US		10000
 #define CMD_PKT_STATUS_TIMEOUT_US	20000
@@ -250,6 +198,53 @@ struct dw_mipi_dsi {
 	struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
 
 	const struct dw_mipi_dsi_plat_data *plat_data;
+
+	struct regmap_field	*field_dpi_18loosely_en;
+	struct regmap_field	*field_dpi_color_coding;
+	struct regmap_field	*field_dpi_vid;
+	struct regmap_field	*field_dpi_vsync_active_low;
+	struct regmap_field	*field_dpi_hsync_active_low;
+	struct regmap_field	*field_cmd_mode_ack_rqst_en;
+	struct regmap_field	*field_cmd_mode_all_lp_en;
+	struct regmap_field	*field_cmd_mode_en;
+	struct regmap_field	*field_cmd_pkt_status;
+	struct regmap_field	*field_vid_mode_en;
+	struct regmap_field	*field_vid_mode_type;
+	struct regmap_field	*field_vid_mode_low_power;
+	struct regmap_field	*field_vid_mode_vpg_en;
+	struct regmap_field	*field_vid_mode_vpg_horiz;
+	struct regmap_field	*field_vid_pkt_size;
+	struct regmap_field	*field_vid_hsa_time;
+	struct regmap_field	*field_vid_hbp_time;
+	struct regmap_field	*field_vid_hline_time;
+	struct regmap_field	*field_vid_vsa_time;
+	struct regmap_field	*field_vid_vbp_time;
+	struct regmap_field	*field_vid_vfp_time;
+	struct regmap_field	*field_vid_vactive_time;
+	struct regmap_field	*field_phy_txrequestclkhs;
+	struct regmap_field	*field_phy_bta_time;
+	struct regmap_field	*field_phy_max_rd_time;
+	struct regmap_field	*field_phy_lp2hs_time;
+	struct regmap_field	*field_phy_hs2lp_time;
+	struct regmap_field	*field_phy_clklp2hs_time;
+	struct regmap_field	*field_phy_clkhs2lp_time;
+	struct regmap_field	*field_phy_testclr;
+	struct regmap_field	*field_phy_unshutdownz;
+	struct regmap_field	*field_phy_unrstz;
+	struct regmap_field	*field_phy_enableclk;
+	struct regmap_field	*field_phy_forcepll;
+	struct regmap_field	*field_phy_nlanes;
+	struct regmap_field	*field_phy_stop_wait_time;
+	struct regmap_field	*field_phy_status;
+	struct regmap_field	*field_pckhdl_cfg;
+	struct regmap_field	*field_hstx_timeout_counter;
+	struct regmap_field	*field_lprx_timeout_counter;
+	struct regmap_field	*field_int_stat0;
+	struct regmap_field	*field_int_stat1;
+	struct regmap_field	*field_int_mask0;
+	struct regmap_field	*field_int_mask1;
+	struct regmap_field	*field_gen_hdr;
+	struct regmap_field	*field_gen_payload;
 };
 
 static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
@@ -259,6 +254,111 @@ static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
 	.name = "dw-mipi-dsi",
 };
 
+struct dw_mipi_dsi_variant {
+	/* Regmap field configs for DSI adapter */
+	struct reg_field	cfg_dpi_18loosely_en;
+	struct reg_field	cfg_dpi_color_coding;
+	struct reg_field	cfg_dpi_vid;
+	struct reg_field	cfg_dpi_vsync_active_low;
+	struct reg_field	cfg_dpi_hsync_active_low;
+	struct reg_field	cfg_cmd_mode_en;
+	struct reg_field	cfg_cmd_mode_ack_rqst_en;
+	struct reg_field	cfg_cmd_mode_all_lp_en;
+	struct reg_field	cfg_cmd_pkt_status;
+	struct reg_field	cfg_vid_mode_en;
+	struct reg_field	cfg_vid_mode_type;
+	struct reg_field	cfg_vid_mode_low_power;
+	struct reg_field	cfg_vid_mode_vpg_en;
+	struct reg_field	cfg_vid_mode_vpg_horiz;
+	struct reg_field	cfg_vid_pkt_size;
+	struct reg_field	cfg_vid_hsa_time;
+	struct reg_field	cfg_vid_hbp_time;
+	struct reg_field	cfg_vid_hline_time;
+	struct reg_field	cfg_vid_vsa_time;
+	struct reg_field	cfg_vid_vbp_time;
+	struct reg_field	cfg_vid_vfp_time;
+	struct reg_field	cfg_vid_vactive_time;
+	struct reg_field	cfg_phy_txrequestclkhs;
+	struct reg_field	cfg_phy_bta_time;
+	struct reg_field	cfg_phy_max_rd_time;
+	struct reg_field	cfg_phy_lp2hs_time;
+	struct reg_field	cfg_phy_hs2lp_time;
+	struct reg_field	cfg_phy_max_rd_time_v131;
+	struct reg_field	cfg_phy_lp2hs_time_v131;
+	struct reg_field	cfg_phy_hs2lp_time_v131;
+	struct reg_field	cfg_phy_clklp2hs_time;
+	struct reg_field	cfg_phy_clkhs2lp_time;
+	struct reg_field	cfg_phy_testclr;
+	struct reg_field	cfg_phy_unshutdownz;
+	struct reg_field	cfg_phy_unrstz;
+	struct reg_field	cfg_phy_enableclk;
+	struct reg_field	cfg_phy_forcepll;
+	struct reg_field	cfg_phy_nlanes;
+	struct reg_field	cfg_phy_stop_wait_time;
+	struct reg_field	cfg_phy_status;
+	struct reg_field	cfg_pckhdl_cfg;
+	struct reg_field	cfg_hstx_timeout_counter;
+	struct reg_field	cfg_lprx_timeout_counter;
+	struct reg_field	cfg_int_stat0;
+	struct reg_field	cfg_int_stat1;
+	struct reg_field	cfg_int_mask0;
+	struct reg_field	cfg_int_mask1;
+	struct reg_field	cfg_gen_hdr;
+	struct reg_field	cfg_gen_payload;
+};
+
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
+	.cfg_dpi_color_coding =		REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
+	.cfg_dpi_18loosely_en =		REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
+	.cfg_dpi_vid =			REG_FIELD(DSI_DPI_VCID, 0, 2),
+	.cfg_dpi_vsync_active_low =	REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
+	.cfg_dpi_hsync_active_low =	REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
+	.cfg_cmd_mode_ack_rqst_en =	REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
+	.cfg_cmd_mode_all_lp_en =	REG_FIELD(DSI_CMD_MODE_CFG, 8, 24),
+	.cfg_cmd_mode_en =		REG_FIELD(DSI_MODE_CFG, 0, 31),
+	.cfg_cmd_pkt_status =		REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
+	.cfg_vid_mode_en =		REG_FIELD(DSI_MODE_CFG, 0, 31),
+	.cfg_vid_mode_type =		REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
+	.cfg_vid_mode_low_power =	REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
+	.cfg_vid_mode_vpg_en =		REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
+	.cfg_vid_mode_vpg_horiz =	REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
+	.cfg_vid_pkt_size =		REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
+	.cfg_vid_hsa_time =		REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
+	.cfg_vid_hbp_time =		REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
+	.cfg_vid_hline_time =		REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
+	.cfg_vid_vsa_time =		REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
+	.cfg_vid_vbp_time =		REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
+	.cfg_vid_vfp_time =		REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
+	.cfg_vid_vactive_time =		REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
+	.cfg_phy_txrequestclkhs =	REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
+	.cfg_phy_bta_time =		REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
+	.cfg_phy_max_rd_time =		REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
+	.cfg_phy_lp2hs_time =		REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
+	.cfg_phy_hs2lp_time =		REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
+	.cfg_phy_max_rd_time_v131 =	REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
+	.cfg_phy_lp2hs_time_v131 =	REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
+	.cfg_phy_hs2lp_time_v131 =	REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
+	.cfg_phy_clklp2hs_time =	REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
+	.cfg_phy_clkhs2lp_time =	REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 31),
+	.cfg_phy_testclr =		REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0),
+	.cfg_phy_unshutdownz =		REG_FIELD(DSI_PHY_RSTZ, 0, 0),
+	.cfg_phy_unrstz =		REG_FIELD(DSI_PHY_RSTZ, 1, 1),
+	.cfg_phy_enableclk =		REG_FIELD(DSI_PHY_RSTZ, 2, 2),
+	.cfg_phy_forcepll =		REG_FIELD(DSI_PHY_RSTZ, 3, 3),
+	.cfg_phy_nlanes =		REG_FIELD(DSI_PHY_IF_CFG, 0, 1),
+	.cfg_phy_stop_wait_time =	REG_FIELD(DSI_PHY_IF_CFG, 8, 15),
+	.cfg_phy_status =		REG_FIELD(DSI_PHY_STATUS, 0, 2),
+	.cfg_pckhdl_cfg =		REG_FIELD(DSI_PCKHDL_CFG, 0, 4),
+	.cfg_hstx_timeout_counter =	REG_FIELD(DSI_TO_CNT_CFG, 16, 31),
+	.cfg_lprx_timeout_counter =	REG_FIELD(DSI_TO_CNT_CFG, 0, 15),
+	.cfg_int_stat0 =		REG_FIELD(DSI_INT_ST0, 0, 31),
+	.cfg_int_stat1 =		REG_FIELD(DSI_INT_ST1, 0, 31),
+	.cfg_int_mask0 =		REG_FIELD(DSI_INT_MSK0, 0, 31),
+	.cfg_int_mask1 =		REG_FIELD(DSI_INT_MSK1, 0, 31),
+	.cfg_gen_hdr =			REG_FIELD(DSI_GEN_HDR, 0, 31),
+	.cfg_gen_payload =		REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
+};
+
 /*
  * Check if either a link to a master or slave is present
  */
@@ -359,15 +459,22 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 				   const struct mipi_dsi_msg *msg)
 {
 	bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
-	u32 val = 0;
+	u32 cmd_mode_lp = 0;
+
+	switch (dsi->hw_version) {
+	case HWVER_130:
+	case HWVER_131:
+		cmd_mode_lp = CMD_MODE_ALL_LP;
+		break;
+	}
 
 	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
-		val |= ACK_RQST_EN;
+		regmap_field_write(dsi->field_cmd_mode_ack_rqst_en, 1);
+
 	if (lpm)
-		val |= CMD_MODE_ALL_LP;
+		regmap_field_write(dsi->field_cmd_mode_all_lp_en, cmd_mode_lp);
 
-	regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
-	regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
+	regmap_field_write(dsi->field_phy_txrequestclkhs, lpm ? 0 : 1);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
@@ -375,18 +482,18 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 	int ret;
 	u32 val = 0, mask;
 
-	ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
-				       val, !(val & GEN_CMD_FULL), 1000,
-				       CMD_PKT_STATUS_TIMEOUT_US);
+	ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
+					     val, !(val & GEN_CMD_FULL),
+					     1000, CMD_PKT_STATUS_TIMEOUT_US);
 	if (ret) {
 		dev_err(dsi->dev, "failed to get available command FIFO\n");
 		return ret;
 	}
 
-	regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
+	regmap_field_write(dsi->field_gen_hdr, hdr_val);
 
 	mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-	ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+	ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
 				       val, (val & mask) == mask,
 				       1000, CMD_PKT_STATUS_TIMEOUT_US);
 	if (ret) {
@@ -409,20 +516,22 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
 		if (len < pld_data_bytes) {
 			word = 0;
 			memcpy(&word, tx_buf, len);
-			regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
-				     le32_to_cpu(word));
+			regmap_field_force_write(dsi->field_gen_payload,
+						 le32_to_cpu(word));
 			len = 0;
 		} else {
 			memcpy(&word, tx_buf, pld_data_bytes);
-			regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
-				     le32_to_cpu(word));
+			regmap_field_force_write(dsi->field_gen_payload,
+						 le32_to_cpu(word));
 			tx_buf += pld_data_bytes;
 			len -= pld_data_bytes;
 		}
 
-		ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
-					       val, !(val & GEN_PLD_W_FULL),
-					       1000, CMD_PKT_STATUS_TIMEOUT_US);
+		ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
+						     val,
+						     !(val & GEN_PLD_W_FULL),
+						     1000,
+						     CMD_PKT_STATUS_TIMEOUT_US);
 		if (ret) {
 			dev_err(dsi->dev,
 				"failed to get available write payload FIFO\n");
@@ -443,9 +552,9 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
 	u32 val = 0;
 
 	/* Wait end of the read operation */
-	ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
-				       val, !(val & GEN_RD_CMD_BUSY),
-				       1000, CMD_PKT_STATUS_TIMEOUT_US);
+	ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
+					     val, !(val & GEN_RD_CMD_BUSY),
+					     1000, CMD_PKT_STATUS_TIMEOUT_US);
 	if (ret) {
 		dev_err(dsi->dev, "Timeout during read operation\n");
 		return ret;
@@ -453,15 +562,17 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
 
 	for (i = 0; i < len; i += 4) {
 		/* Read fifo must not be empty before all bytes are read */
-		ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
-					       val, !(val & GEN_PLD_R_EMPTY),
-					       1000, CMD_PKT_STATUS_TIMEOUT_US);
+		ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
+						     val,
+						     !(val & GEN_PLD_R_EMPTY),
+						     1000,
+						     CMD_PKT_STATUS_TIMEOUT_US);
 		if (ret) {
 			dev_err(dsi->dev, "Read payload FIFO is empty\n");
 			return ret;
 		}
 
-		regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val);
+		regmap_field_read(dsi->field_gen_payload, &val);
 		for (j = 0; j < 4 && j + i < len; j++)
 			buf[i + j] = val >> (8 * j);
 	}
@@ -515,30 +626,30 @@ static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 
 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 {
-	u32 val;
-
 	/*
 	 * TODO dw drv improvements
 	 * enabling low power is panel-dependent, we should use the
 	 * panel configuration here...
 	 */
-	val = ENABLE_LOW_POWER;
+	regmap_field_write(dsi->field_vid_mode_low_power, ENABLE_LOW_POWER);
 
 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
-		val |= VID_MODE_TYPE_BURST;
+		regmap_field_write(dsi->field_vid_mode_type,
+				   VID_MODE_TYPE_BURST);
 	else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-		val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
+		regmap_field_write(dsi->field_vid_mode_type,
+				   VID_MODE_TYPE_NON_BURST_SYNC_PULSES);
 	else
-		val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
+		regmap_field_write(dsi->field_vid_mode_type,
+				   VID_MODE_TYPE_NON_BURST_SYNC_EVENTS);
 
 #ifdef CONFIG_DEBUG_FS
 	if (dsi->vpg) {
-		val |= VID_MODE_VPG_ENABLE;
-		val |= dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0;
+		regmap_field_write(dsi->field_vid_mode_vpg_en, 1);
+		regmap_field_write(dsi->field_vid_mode_vpg_horiz,
+				   dsi->vpg_horizontal ? 1 : 0);
 	}
 #endif /* CONFIG_DEBUG_FS */
-
-	regmap_write(dsi->regs, DSI_VID_MODE_CFG, val);
 }
 
 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
@@ -547,11 +658,13 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 	regmap_write(dsi->regs, DSI_PWR_UP, RESET);
 
 	if (mode_flags & MIPI_DSI_MODE_VIDEO) {
-		regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
+		regmap_field_write(dsi->field_cmd_mode_en, 0);
+
 		dw_mipi_dsi_video_mode_config(dsi);
-		regmap_write(dsi->regs, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
+
+		regmap_field_write(dsi->field_phy_txrequestclkhs, 1);
 	} else {
-		regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
+		regmap_field_write(dsi->field_cmd_mode_en, 1);
 	}
 
 	regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
@@ -560,7 +673,7 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 {
 	regmap_write(dsi->regs, DSI_PWR_UP, RESET);
-	regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ);
+	regmap_field_write(dsi->field_phy_unrstz, 0);
 }
 
 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
@@ -589,14 +702,15 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 				   const struct drm_display_mode *mode)
 {
-	u32 val = 0, color = 0;
+	u32 color = 0;
 
 	switch (dsi->format) {
 	case MIPI_DSI_FMT_RGB888:
 		color = DPI_COLOR_CODING_24BIT;
 		break;
 	case MIPI_DSI_FMT_RGB666:
-		color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
+		color = DPI_COLOR_CODING_18BIT_2;
+		regmap_field_write(dsi->field_dpi_18loosely_en, 1);
 		break;
 	case MIPI_DSI_FMT_RGB666_PACKED:
 		color = DPI_COLOR_CODING_18BIT_1;
@@ -606,14 +720,14 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 		break;
 	}
 
+	regmap_field_write(dsi->field_dpi_vid, DPI_VCID(dsi->channel));
+	regmap_field_write(dsi->field_dpi_color_coding, color);
+
 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
-		val |= VSYNC_ACTIVE_LOW;
+		regmap_field_write(dsi->field_dpi_vsync_active_low, 1);
 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
-		val |= HSYNC_ACTIVE_LOW;
+		regmap_field_write(dsi->field_dpi_hsync_active_low, 1);
 
-	regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel));
-	regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color);
-	regmap_write(dsi->regs, DSI_DPI_CFG_POL, val);
 	/*
 	 * TODO dw drv improvements
 	 * largest packet sizes during hfp or during vsa/vpb/vfp
@@ -626,7 +740,8 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 
 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 {
-	regmap_write(dsi->regs, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
+	regmap_field_write(dsi->field_pckhdl_cfg,
+			   CRC_RX_EN | ECC_RX_EN | BTA_EN);
 }
 
 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
@@ -639,11 +754,9 @@ static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 	 * DSI_VNPCR.NPSIZE... especially because this driver supports
 	 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
 	 */
-
-	regmap_write(dsi->regs, DSI_VID_PKT_SIZE,
-		       dw_mipi_is_dual_mode(dsi) ?
-				VID_PKT_SIZE(mode->hdisplay / 2) :
-				VID_PKT_SIZE(mode->hdisplay));
+	regmap_field_write(dsi->field_vid_pkt_size,
+			   dw_mipi_is_dual_mode(dsi) ?
+				mode->hdisplay / 2 : mode->hdisplay);
 }
 
 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
@@ -653,15 +766,17 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 	 * compute high speed transmission counter timeout according
 	 * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
 	 */
-	regmap_write(dsi->regs, DSI_TO_CNT_CFG,
-		     HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
+	regmap_field_write(dsi->field_hstx_timeout_counter, 1000);
+	regmap_field_write(dsi->field_lprx_timeout_counter, 1000);
+
 	/*
 	 * TODO dw drv improvements
 	 * the Bus-Turn-Around Timeout Counter should be computed
 	 * according to byte lane...
 	 */
-	regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00);
-	regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
+	regmap_field_write(dsi->field_phy_bta_time, 0xd00);
+
+	regmap_field_write(dsi->field_cmd_mode_en, 1);
 }
 
 /* Get lane byte clock cycles. */
@@ -695,13 +810,13 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
 	 * computations below may be improved...
 	 */
 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
-	regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc);
+	regmap_field_write(dsi->field_vid_hline_time, lbcc);
 
 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
-	regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc);
+	regmap_field_write(dsi->field_vid_hsa_time, lbcc);
 
 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
-	regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc);
+	regmap_field_write(dsi->field_vid_hbp_time, lbcc);
 }
 
 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
@@ -714,17 +829,16 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
 	vfp = mode->vsync_start - mode->vdisplay;
 	vbp = mode->vtotal - mode->vsync_end;
 
-	regmap_write(dsi->regs, DSI_VID_VACTIVE_LINES, vactive);
-	regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa);
-	regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp);
-	regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp);
+	regmap_field_write(dsi->field_vid_vactive_time, vactive);
+	regmap_field_write(dsi->field_vid_vsa_time, vsa);
+	regmap_field_write(dsi->field_vid_vfp_time, vfp);
+	regmap_field_write(dsi->field_vid_vbp_time, vbp);
 }
 
 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 {
 	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
 	struct dw_mipi_dsi_dphy_timing timing;
-	u32 hw_version;
 	int ret;
 
 	ret = phy_ops->get_timing(dsi->plat_data->priv_data,
@@ -739,26 +853,12 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 	 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
 	 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
 	 */
+	regmap_field_write(dsi->field_phy_lp2hs_time, timing.data_lp2hs);
+	regmap_field_write(dsi->field_phy_hs2lp_time, timing.data_hs2lp);
 
-	regmap_read(dsi->regs, DSI_VERSION, &hw_version);
-	hw_version &= VERSION;
-
-	if (hw_version >= HWVER_131) {
-		regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
-			     PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
-			     PHY_LP2HS_TIME_V131(timing.data_lp2hs));
-		regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG,
-			     MAX_RD_TIME_V131(10000));
-	} else {
-		regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
-			     PHY_HS2LP_TIME(timing.data_hs2lp) |
-			     PHY_LP2HS_TIME(timing.data_lp2hs) |
-			     MAX_RD_TIME(10000));
-	}
-
-	regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG,
-		     PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
-		     PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
+	regmap_field_write(dsi->field_phy_max_rd_time, 10000);
+	regmap_field_write(dsi->field_phy_clkhs2lp_time, timing.clk_hs2lp);
+	regmap_field_write(dsi->field_phy_clklp2hs_time, timing.clk_lp2hs);
 }
 
 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
@@ -768,18 +868,22 @@ static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 	 * stop wait time should be the maximum between host dsi
 	 * and panel stop wait times
 	 */
-	regmap_write(dsi->regs, DSI_PHY_IF_CFG,
-		     PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes));
+	regmap_field_write(dsi->field_phy_stop_wait_time, 0x20);
+	regmap_field_write(dsi->field_phy_nlanes, dsi->lanes - 1);
 }
 
 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
 {
 	/* Clear PHY state */
-	regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
-		     | PHY_RSTZ | PHY_SHUTDOWNZ);
-	regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
-	regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
-	regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+	regmap_field_write(dsi->field_phy_enableclk, 0);
+	regmap_field_write(dsi->field_phy_unrstz, 0);
+	regmap_field_write(dsi->field_phy_unshutdownz, 0);
+
+	regmap_field_write(dsi->field_phy_forcepll, 0);
+
+	regmap_field_write(dsi->field_phy_testclr, 0);
+	regmap_field_write(dsi->field_phy_testclr, 1);
+	regmap_field_write(dsi->field_phy_testclr, 0);
 }
 
 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
@@ -787,18 +891,21 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
 	u32 val = 0;
 	int ret;
 
-	regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
-		     PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
+	regmap_field_write(dsi->field_phy_enableclk, 1);
+	regmap_field_write(dsi->field_phy_unrstz, 1);
+	regmap_field_write(dsi->field_phy_unshutdownz, 1);
+
+	regmap_field_write(dsi->field_phy_forcepll, 1);
 
-	ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
-				       val, val & PHY_LOCK,
-				       1000, PHY_STATUS_TIMEOUT_US);
+	ret = regmap_field_read_poll_timeout(dsi->field_phy_status,
+					     val, val & PHY_LOCK,
+					     1000, PHY_STATUS_TIMEOUT_US);
 	if (ret)
 		DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
 
-	ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
-				       val, val & PHY_STOP_STATE_CLK_LANE, 1000,
-				       PHY_STATUS_TIMEOUT_US);
+	ret = regmap_field_read_poll_timeout(dsi->field_phy_status,
+					     val, val & PHY_STOP_STATE_CLK_LANE,
+					     1000, PHY_STATUS_TIMEOUT_US);
 	if (ret)
 		DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
 }
@@ -807,10 +914,10 @@ static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 {
 	u32 val;
 
-	regmap_read(dsi->regs, DSI_INT_ST0, &val);
-	regmap_read(dsi->regs, DSI_INT_ST1, &val);
-	regmap_write(dsi->regs, DSI_INT_MSK0, 0);
-	regmap_write(dsi->regs, DSI_INT_MSK1, 0);
+	regmap_field_read(dsi->field_int_stat0, &val);
+	regmap_field_read(dsi->field_int_stat1, &val);
+	regmap_field_write(dsi->field_int_mask0, 0);
+	regmap_field_write(dsi->field_int_mask1, 0);
 }
 
 static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
@@ -1005,6 +1112,84 @@ static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi *dsi)
 		dev_err(dsi->dev, "Failed to read DSI hw version register\n");
 }
 
+#define INIT_FIELD(f) INIT_FIELD_CFG(field_##f, cfg_##f)
+#define INIT_FIELD_CFG(f, conf)	({					\
+		dsi->f = devm_regmap_field_alloc(dsi->dev, dsi->regs,	\
+						 variant->conf);	\
+		if (IS_ERR(dsi->f))					\
+			dev_warn(dsi->dev, "Ignoring regmap field " #f "\n"); })
+
+static int dw_mipi_dsi_regmap_fields_init(struct dw_mipi_dsi *dsi)
+{
+	const struct dw_mipi_dsi_variant *variant;
+
+	switch (dsi->hw_version) {
+	case HWVER_130:
+	case HWVER_131:
+		variant = &dw_mipi_dsi_v130_v131_layout;
+		break;
+	default:
+		DRM_ERROR("Unrecognized DSI host controller HW revision\n");
+		return -ENODEV;
+	}
+
+	INIT_FIELD(dpi_18loosely_en);
+	INIT_FIELD(dpi_vid);
+	INIT_FIELD(dpi_color_coding);
+	INIT_FIELD(dpi_vsync_active_low);
+	INIT_FIELD(dpi_hsync_active_low);
+	INIT_FIELD(cmd_mode_ack_rqst_en);
+	INIT_FIELD(cmd_mode_all_lp_en);
+	INIT_FIELD(cmd_mode_en);
+	INIT_FIELD(cmd_pkt_status);
+	INIT_FIELD(vid_mode_en);
+	INIT_FIELD(vid_mode_type);
+	INIT_FIELD(vid_mode_low_power);
+	INIT_FIELD(vid_pkt_size);
+	INIT_FIELD(vid_hsa_time);
+	INIT_FIELD(vid_hbp_time);
+	INIT_FIELD(vid_hline_time);
+	INIT_FIELD(vid_vsa_time);
+	INIT_FIELD(vid_vbp_time);
+	INIT_FIELD(vid_vfp_time);
+	INIT_FIELD(vid_vactive_time);
+	INIT_FIELD(phy_txrequestclkhs);
+	INIT_FIELD(phy_testclr);
+	INIT_FIELD(phy_unshutdownz);
+	INIT_FIELD(phy_unrstz);
+	INIT_FIELD(phy_enableclk);
+	INIT_FIELD(phy_nlanes);
+	INIT_FIELD(phy_stop_wait_time);
+	INIT_FIELD(phy_status);
+	INIT_FIELD(pckhdl_cfg);
+	INIT_FIELD(hstx_timeout_counter);
+	INIT_FIELD(lprx_timeout_counter);
+	INIT_FIELD(int_stat0);
+	INIT_FIELD(int_stat1);
+	INIT_FIELD(int_mask0);
+	INIT_FIELD(int_mask1);
+	INIT_FIELD(gen_hdr);
+	INIT_FIELD(gen_payload);
+	INIT_FIELD(phy_bta_time);
+	INIT_FIELD(vid_mode_vpg_en);
+	INIT_FIELD(vid_mode_vpg_horiz);
+	INIT_FIELD(phy_clklp2hs_time);
+	INIT_FIELD(phy_clkhs2lp_time);
+	INIT_FIELD(phy_forcepll);
+
+	if (dsi->hw_version == HWVER_131) {
+		INIT_FIELD_CFG(field_phy_max_rd_time, cfg_phy_max_rd_time_v131);
+		INIT_FIELD_CFG(field_phy_lp2hs_time, cfg_phy_lp2hs_time_v131);
+		INIT_FIELD_CFG(field_phy_hs2lp_time, cfg_phy_hs2lp_time_v131);
+	} else {
+		INIT_FIELD(phy_max_rd_time);
+		INIT_FIELD(phy_lp2hs_time);
+		INIT_FIELD(phy_hs2lp_time);
+	}
+
+	return 0;
+}
+
 static struct dw_mipi_dsi *
 __dw_mipi_dsi_probe(struct platform_device *pdev,
 		    const struct dw_mipi_dsi_plat_data *plat_data)
@@ -1081,6 +1266,12 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
 
 	dw_mipi_dsi_get_hw_version(dsi);
 
+	ret = dw_mipi_dsi_regmap_fields_init(dsi);
+	if (ret) {
+		dev_err(dev, "Failed to init register layout map: %d\n", ret);
+		return ERR_PTR(ret);
+	}
+
 	dw_mipi_dsi_debugfs_init(dsi);
 	pm_runtime_enable(dev);
 
-- 
2.26.0

[PATCH v6 3/8] drm: bridge: synopsis: add dsi v1.01 support

[Adrian Ratiu]

The Synopsis MIPI DSI v1.01 host controller is quite widely used
on platforms like i.mx6 and is not very different from the other
versions like the 1.31/1.30 used on rockchip/stm. The protocols
appear to be the same, only the register layout is different and
the newer versions have new features symbolized by new registers
so adding support for it is just a matter of defining the new
layout and adding a couple of dsi version checks.

Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Signed-off-by: Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
Changes since v5:
  - Fixed cfg_phy_status range from [0,0] to [0,2]

New in v5.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +++++++++++++++++-
 1 file changed, 119 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index f72643e25669..0ce2697d17a3 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -32,6 +32,7 @@
 
 #define HWVER_131			0x31333100	/* IP version 1.31 */
 #define HWVER_130			0x31333000	/* IP version 1.30 */
+#define HWVER_101			0x31303000	/* IP version 1.01 */
 
 #define DSI_VERSION			0x00
 #define VERSION				GENMASK(31, 8)
@@ -100,6 +101,25 @@
 #define DSI_EDPI_CMD_SIZE		0x64
 
 #define DSI_CMD_MODE_CFG		0x68
+
+#define DSI_DPI_CFG			0x0c
+#define DSI_TMR_LINE_CFG		0x28
+#define DSI_VTIMING_CFG			0x2c
+#define DSI_PHY_TMR_CFG_V101		0x30
+#define DSI_PHY_IF_CFG_V101		0x58
+#define DSI_PHY_IF_CTRL			0x5c
+#define DSI_PHY_RSTZ_V101		0x54
+#define DSI_PHY_STATUS_V101		0x60
+#define DSI_PHY_TST_CTRL0_V101		0x64
+#define DSI_GEN_HDR_V101		0x34
+#define DSI_GEN_PLD_DATA_V101		0x38
+#define DSI_CMD_MODE_CFG_V101		0x24
+#define DSI_CMD_PKT_STATUS_V101		0x3c
+#define DSI_VID_PKT_CFG			0x20
+#define DSI_VID_MODE_CFG_V101		0x1c
+#define DSI_TO_CNT_CFG_V101		0x40
+#define DSI_PCKHDL_CFG_V101		0x18
+
 #define MAX_RD_PKT_SIZE_LP		BIT(24)
 #define DCS_LW_TX_LP			BIT(19)
 #define DCS_SR_0P_TX_LP			BIT(18)
@@ -127,6 +147,33 @@
 					 GEN_SW_1P_TX_LP | \
 					 GEN_SW_0P_TX_LP)
 
+#define EN_TEAR_FX_V101			BIT(14)
+#define DCS_LW_TX_LP_V101		BIT(12)
+#define GEN_LW_TX_LP_V101		BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101		BIT(10)
+#define DCS_SW_2P_TX_LP_V101		BIT(9)
+#define DCS_SW_1P_TX_LP_V101		BIT(8)
+#define DCS_SW_0P_TX_LP_V101		BIT(7)
+#define GEN_SR_2P_TX_LP_V101		BIT(6)
+#define GEN_SR_1P_TX_LP_V101		BIT(5)
+#define GEN_SR_0P_TX_LP_V101		BIT(4)
+#define GEN_SW_2P_TX_LP_V101		BIT(3)
+#define GEN_SW_1P_TX_LP_V101		BIT(2)
+#define GEN_SW_0P_TX_LP_V101		BIT(1)
+
+#define CMD_MODE_ALL_LP_V101		(DCS_LW_TX_LP_V101 | \
+					 GEN_LW_TX_LP_V101 | \
+					 MAX_RD_PKT_SIZE_LP_V101 | \
+					 DCS_SW_2P_TX_LP_V101 | \
+					 DCS_SW_1P_TX_LP_V101 | \
+					 DCS_SW_0P_TX_LP_V101 | \
+					 GEN_SR_2P_TX_LP_V101 | \
+					 GEN_SR_1P_TX_LP_V101 | \
+					 GEN_SR_0P_TX_LP_V101 | \
+					 GEN_SW_2P_TX_LP_V101 | \
+					 GEN_SW_1P_TX_LP_V101 | \
+					 GEN_SW_0P_TX_LP_V101)
+
 #define DSI_GEN_HDR			0x6c
 #define DSI_GEN_PLD_DATA		0x70
 
@@ -165,6 +212,11 @@
 #define DSI_INT_MSK0			0xc4
 #define DSI_INT_MSK1			0xc8
 
+#define DSI_ERROR_ST0_V101		0x44
+#define DSI_ERROR_ST1_V101		0x48
+#define DSI_ERROR_MSK0_V101		0x4c
+#define DSI_ERROR_MSK1_V101		0x50
+
 #define DSI_PHY_TMR_RD_CFG		0xf4
 
 #define PHY_STATUS_TIMEOUT_US		10000
@@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
 	.cfg_gen_payload =		REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
 };
 
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+	.cfg_dpi_vid =			REG_FIELD(DSI_DPI_CFG, 0, 1),
+	.cfg_dpi_color_coding =		REG_FIELD(DSI_DPI_CFG, 2, 4),
+	.cfg_dpi_18loosely_en =		REG_FIELD(DSI_DPI_CFG, 10, 10),
+	.cfg_dpi_vsync_active_low =	REG_FIELD(DSI_DPI_CFG, 6, 6),
+	.cfg_dpi_hsync_active_low =	REG_FIELD(DSI_DPI_CFG, 7, 7),
+	.cfg_cmd_mode_en =		REG_FIELD(DSI_CMD_MODE_CFG_V101, 0, 0),
+	.cfg_cmd_mode_all_lp_en =	REG_FIELD(DSI_CMD_MODE_CFG_V101, 1, 12),
+	.cfg_cmd_mode_ack_rqst_en =	REG_FIELD(DSI_CMD_MODE_CFG_V101, 13, 13),
+	.cfg_cmd_pkt_status =		REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 14),
+	.cfg_vid_mode_en =		REG_FIELD(DSI_VID_MODE_CFG_V101, 0, 0),
+	.cfg_vid_mode_type =		REG_FIELD(DSI_VID_MODE_CFG_V101, 1, 2),
+	.cfg_vid_mode_low_power =	REG_FIELD(DSI_VID_MODE_CFG_V101, 3, 8),
+	.cfg_vid_pkt_size =		REG_FIELD(DSI_VID_PKT_CFG, 0, 10),
+	.cfg_vid_hsa_time =		REG_FIELD(DSI_TMR_LINE_CFG, 0, 8),
+	.cfg_vid_hbp_time =		REG_FIELD(DSI_TMR_LINE_CFG, 9, 17),
+	.cfg_vid_hline_time =		REG_FIELD(DSI_TMR_LINE_CFG, 18, 31),
+	.cfg_vid_vsa_time =		REG_FIELD(DSI_VTIMING_CFG, 0, 3),
+	.cfg_vid_vbp_time =		REG_FIELD(DSI_VTIMING_CFG, 4, 9),
+	.cfg_vid_vfp_time =		REG_FIELD(DSI_VTIMING_CFG, 10, 15),
+	.cfg_vid_vactive_time =		REG_FIELD(DSI_VTIMING_CFG, 16, 26),
+	.cfg_phy_txrequestclkhs =	REG_FIELD(DSI_PHY_IF_CTRL, 0, 0),
+	.cfg_phy_bta_time =		REG_FIELD(DSI_PHY_TMR_CFG_V101, 0, 11),
+	.cfg_phy_lp2hs_time =		REG_FIELD(DSI_PHY_TMR_CFG_V101, 12, 19),
+	.cfg_phy_hs2lp_time =		REG_FIELD(DSI_PHY_TMR_CFG_V101, 20, 27),
+	.cfg_phy_testclr =		REG_FIELD(DSI_PHY_TST_CTRL0_V101, 0, 0),
+	.cfg_phy_unshutdownz =		REG_FIELD(DSI_PHY_RSTZ_V101, 0, 0),
+	.cfg_phy_unrstz =		REG_FIELD(DSI_PHY_RSTZ_V101, 1, 1),
+	.cfg_phy_enableclk =		REG_FIELD(DSI_PHY_RSTZ_V101, 2, 2),
+	.cfg_phy_nlanes =		REG_FIELD(DSI_PHY_IF_CFG_V101, 0, 1),
+	.cfg_phy_stop_wait_time =	REG_FIELD(DSI_PHY_IF_CFG_V101, 2, 9),
+	.cfg_phy_status =		REG_FIELD(DSI_PHY_STATUS_V101, 0, 2),
+	.cfg_pckhdl_cfg =		REG_FIELD(DSI_PCKHDL_CFG_V101, 0, 4),
+	.cfg_hstx_timeout_counter =	REG_FIELD(DSI_TO_CNT_CFG_V101, 0, 15),
+	.cfg_lprx_timeout_counter =	REG_FIELD(DSI_TO_CNT_CFG_V101, 16, 31),
+	.cfg_int_stat0 =		REG_FIELD(DSI_ERROR_ST0_V101, 0, 20),
+	.cfg_int_stat1 =		REG_FIELD(DSI_ERROR_ST1_V101, 0, 17),
+	.cfg_int_mask0 =		REG_FIELD(DSI_ERROR_MSK0_V101, 0, 20),
+	.cfg_int_mask1 =		REG_FIELD(DSI_ERROR_MSK1_V101, 0, 17),
+	.cfg_gen_hdr =			REG_FIELD(DSI_GEN_HDR_V101, 0, 31),
+	.cfg_gen_payload =		REG_FIELD(DSI_GEN_PLD_DATA_V101, 0, 31),
+};
+
 /*
  * Check if either a link to a master or slave is present
  */
@@ -466,6 +561,9 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 	case HWVER_131:
 		cmd_mode_lp = CMD_MODE_ALL_LP;
 		break;
+	case HWVER_101:
+		cmd_mode_lp = CMD_MODE_ALL_LP_V101;
+		break;
 	}
 
 	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
@@ -644,7 +742,7 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 				   VID_MODE_TYPE_NON_BURST_SYNC_EVENTS);
 
 #ifdef CONFIG_DEBUG_FS
-	if (dsi->vpg) {
+	if (dsi->hw_version > HWVER_101 && dsi->vpg) {
 		regmap_field_write(dsi->field_vid_mode_vpg_en, 1);
 		regmap_field_write(dsi->field_vid_mode_vpg_horiz,
 				   dsi->vpg_horizontal ? 1 : 0);
@@ -662,9 +760,15 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 
 		dw_mipi_dsi_video_mode_config(dsi);
 
+		if (dsi->hw_version == HWVER_101)
+			regmap_field_write(dsi->field_vid_mode_en, 1);
+
 		regmap_field_write(dsi->field_phy_txrequestclkhs, 1);
 	} else {
 		regmap_field_write(dsi->field_cmd_mode_en, 1);
+
+		if (dsi->hw_version == HWVER_101)
+			regmap_field_write(dsi->field_vid_mode_en, 0);
 	}
 
 	regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
@@ -856,9 +960,13 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 	regmap_field_write(dsi->field_phy_lp2hs_time, timing.data_lp2hs);
 	regmap_field_write(dsi->field_phy_hs2lp_time, timing.data_hs2lp);
 
-	regmap_field_write(dsi->field_phy_max_rd_time, 10000);
-	regmap_field_write(dsi->field_phy_clkhs2lp_time, timing.clk_hs2lp);
-	regmap_field_write(dsi->field_phy_clklp2hs_time, timing.clk_lp2hs);
+	if (dsi->hw_version > HWVER_101) {
+		regmap_field_write(dsi->field_phy_max_rd_time, 10000);
+		regmap_field_write(dsi->field_phy_clkhs2lp_time,
+				   timing.clk_hs2lp);
+		regmap_field_write(dsi->field_phy_clklp2hs_time,
+				   timing.clk_lp2hs);
+	}
 }
 
 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
@@ -879,7 +987,8 @@ static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
 	regmap_field_write(dsi->field_phy_unrstz, 0);
 	regmap_field_write(dsi->field_phy_unshutdownz, 0);
 
-	regmap_field_write(dsi->field_phy_forcepll, 0);
+	if (dsi->hw_version > HWVER_101)
+		regmap_field_write(dsi->field_phy_forcepll, 0);
 
 	regmap_field_write(dsi->field_phy_testclr, 0);
 	regmap_field_write(dsi->field_phy_testclr, 1);
@@ -895,7 +1004,8 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
 	regmap_field_write(dsi->field_phy_unrstz, 1);
 	regmap_field_write(dsi->field_phy_unshutdownz, 1);
 
-	regmap_field_write(dsi->field_phy_forcepll, 1);
+	if (dsi->hw_version > HWVER_101)
+		regmap_field_write(dsi->field_phy_forcepll, 1);
 
 	ret = regmap_field_read_poll_timeout(dsi->field_phy_status,
 					     val, val & PHY_LOCK,
@@ -1128,6 +1238,9 @@ static int dw_mipi_dsi_regmap_fields_init(struct dw_mipi_dsi *dsi)
 	case HWVER_131:
 		variant = &dw_mipi_dsi_v130_v131_layout;
 		break;
+	case HWVER_101:
+		variant = &dw_mipi_dsi_v101_layout;
+		break;
 	default:
 		DRM_ERROR("Unrecognized DSI host controller HW revision\n");
 		return -ENODEV;
-- 
2.26.0

[PATCH v6 4/8] drm: imx: Add i.MX 6 MIPI DSI host platform driver

[Adrian Ratiu]

This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
controller which is embedded in i.MX 6 SoCs.

Based on following patches, but updated/extended to work with existing
support found in the kernel:

- drm: imx: Support Synopsys DesignWare MIPI DSI host controller
  Signed-off-by: Liu Ying <Ying.Liu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>

Cc: Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Emil Velikov <emil.velikov-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Signed-off-by: Sjoerd Simons <sjoerd.simons-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Signed-off-by: Martyn Welch <martyn.welch-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Signed-off-by: Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
Changes since v5:
  - Reword to remove unrelated device tree patch mention (Fabio)
  - Move pllref_clk enable/disable to bind/unbind (Ezequiel)
  - Fix freescale.com -> nxp.com email addresses (Fabio)
  - Also added myself as module author (Fabio)
  - Use DRM_DEV_* macros for consistency, print more error msg

Changes since v4:
  - Split off driver-specific configuration of phy timings due
  to new upstream API.
  - Move regmap infrastructure logic to separate commit (Ezequiel)
  - Move dsi v1.01 layout addition to a separate commit (Ezequiel)
  - Minor warnings and driver name fixes

Changes since v3:
  - Renamed platform driver to reflect it's i.MX6 only. (Fabio)

Changes since v2:
  - Fixed commit tags. (Emil)

Changes since v1:
  - Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after
  calling the bridge probe. (Emil)
---
 drivers/gpu/drm/imx/Kconfig            |   7 +
 drivers/gpu/drm/imx/Makefile           |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 409 +++++++++++++++++++++++++
 3 files changed, 417 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 207bf7409dfb..b49e70e7f0fd 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -39,3 +39,10 @@ config DRM_IMX_HDMI
 	depends on DRM_IMX
 	help
 	  Choose this if you want to use HDMI on i.MX6.
+
+config DRM_IMX6_MIPI_DSI
+	tristate "Freescale i.MX6 DRM MIPI DSI"
+	select DRM_DW_MIPI_DSI
+	depends on DRM_IMX
+	help
+	  Choose this if you want to use MIPI DSI on i.MX6.
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 21cdcc2faabc..9a7843c59347 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o
diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
new file mode 100644
index 000000000000..6914db8ce8cb
--- /dev/null
+++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX6 drm driver - MIPI DSI Host Controller
+ *
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2019-2020 Collabora, Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/videodev2.h>
+#include <drm/bridge/dw_mipi_dsi.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+
+#include "imx-drm.h"
+
+#define DSI_PWR_UP			0x04
+#define RESET				0
+#define POWERUP				BIT(0)
+
+#define DSI_PHY_IF_CTRL			0x5c
+#define PHY_IF_CTRL_RESET		0x0
+
+#define DSI_PHY_TST_CTRL0		0x64
+#define PHY_TESTCLK			BIT(1)
+#define PHY_UNTESTCLK			0
+#define PHY_TESTCLR			BIT(0)
+#define PHY_UNTESTCLR			0
+
+#define DSI_PHY_TST_CTRL1		0x68
+#define PHY_TESTEN			BIT(16)
+#define PHY_UNTESTEN			0
+#define PHY_TESTDOUT(n)			(((n) & 0xff) << 8)
+#define PHY_TESTDIN(n)			(((n) & 0xff) << 0)
+
+struct imx_mipi_dsi {
+	struct drm_encoder encoder;
+	struct device *dev;
+	struct regmap *mux_sel;
+	struct dw_mipi_dsi *mipi_dsi;
+	struct clk *pllref_clk;
+
+	void __iomem *base;
+	unsigned int lane_mbps;
+};
+
+struct dphy_pll_testdin_map {
+	unsigned int max_mbps;
+	u8 testdin;
+};
+
+/* The table is based on 27MHz DPHY pll reference clock. */
+static const struct dphy_pll_testdin_map dptdin_map[] = {
+	{160, 0x04}, {180, 0x24}, {200, 0x44}, {210, 0x06},
+	{240, 0x26}, {250, 0x46}, {270, 0x08}, {300, 0x28},
+	{330, 0x48}, {360, 0x2a}, {400, 0x4a}, {450, 0x0c},
+	{500, 0x2c}, {550, 0x0e}, {600, 0x2e}, {650, 0x10},
+	{700, 0x30}, {750, 0x12}, {800, 0x32}, {850, 0x14},
+	{900, 0x34}, {950, 0x54}, {1000, 0x74}
+};
+
+static inline struct imx_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
+{
+	return container_of(enc, struct imx_mipi_dsi, encoder);
+}
+
+static void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, int ipu_di)
+{
+	regmap_update_bits(dsi->mux_sel, IOMUXC_GPR3,
+			   IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
+			   ipu_di << IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT);
+}
+
+static const struct drm_encoder_funcs imx_mipi_dsi_encoder_funcs = {
+	.destroy = imx_drm_encoder_destroy,
+};
+
+static bool imx_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
+					    const struct drm_display_mode *mode,
+					    struct drm_display_mode *adj_mode)
+{
+	return true;
+}
+
+static int imx_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
+					     struct drm_crtc_state *crtc_state,
+					     struct drm_connector_state *conn)
+{
+	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
+
+	/* The following values are taken from dw_hdmi_imx_atomic_check */
+	imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+	imx_crtc_state->di_hsync_pin = 2;
+	imx_crtc_state->di_vsync_pin = 3;
+
+	return 0;
+}
+
+static void imx_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
+{
+	struct imx_mipi_dsi *dsi = enc_to_dsi(encoder);
+	int mux = drm_of_encoder_active_port_id(dsi->dev->of_node, encoder);
+
+	imx_mipi_dsi_set_ipu_di_mux(dsi, mux);
+}
+
+static void imx_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
+{
+}
+
+static const struct drm_encoder_helper_funcs imx_mipi_dsi_encoder_helpers = {
+	.mode_fixup = imx_mipi_dsi_encoder_mode_fixup,
+	.commit = imx_mipi_dsi_encoder_commit,
+	.disable = imx_mipi_dsi_encoder_disable,
+	.atomic_check = imx_mipi_dsi_encoder_atomic_check,
+};
+
+static int imx_mipi_dsi_register(struct drm_device *drm,
+				 struct imx_mipi_dsi *dsi)
+{
+	int ret;
+
+	ret = imx_drm_encoder_parse_of(drm, &dsi->encoder, dsi->dev->of_node);
+	if (ret)
+		return ret;
+
+	drm_encoder_helper_add(&dsi->encoder,
+			       &imx_mipi_dsi_encoder_helpers);
+	drm_encoder_init(drm, &dsi->encoder, &imx_mipi_dsi_encoder_funcs,
+			 DRM_MODE_ENCODER_DSI, NULL);
+	return 0;
+}
+
+static enum drm_mode_status imx_mipi_dsi_mode_valid(void *priv_data,
+					const struct drm_display_mode *mode)
+{
+	/*
+	 * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG
+	 * register is 11-bit.
+	 */
+	if (mode->hdisplay > 0x7ff)
+		return MODE_BAD_HVALUE;
+
+	/*
+	 * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG
+	 * register is 11-bit.
+	 */
+	if (mode->vdisplay > 0x7ff)
+		return MODE_BAD_VVALUE;
+
+	return MODE_OK;
+}
+
+
+static unsigned int max_mbps_to_testdin(unsigned int max_mbps)
+{
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
+		if (dptdin_map[i].max_mbps == max_mbps)
+			return dptdin_map[i].testdin;
+
+	return -EINVAL;
+}
+
+static inline void dsi_write(struct imx_mipi_dsi *dsi, u32 reg, u32 val)
+{
+	writel(val, dsi->base + reg);
+}
+
+static int imx_mipi_dsi_phy_init(void *priv_data)
+{
+	struct imx_mipi_dsi *dsi = priv_data;
+	int testdin;
+
+	testdin = max_mbps_to_testdin(dsi->lane_mbps);
+	if (testdin < 0) {
+		DRM_DEV_ERROR(dsi->dev,
+			      "failed to get testdin for %dmbps lane clock\n",
+			      dsi->lane_mbps);
+		return testdin;
+	}
+
+	dsi_write(dsi, DSI_PHY_IF_CTRL, PHY_IF_CTRL_RESET);
+	dsi_write(dsi, DSI_PWR_UP, POWERUP);
+
+	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
+	dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
+		  PHY_TESTDIN(0x44));
+	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
+	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
+	dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
+		  PHY_TESTDIN(testdin));
+	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
+	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
+
+	return 0;
+}
+
+static int imx_mipi_dsi_get_lane_mbps(void *priv_data,
+				      const struct drm_display_mode *mode,
+				      unsigned long mode_flags, u32 lanes,
+				      u32 format, unsigned int *lane_mbps)
+{
+	struct imx_mipi_dsi *dsi = priv_data;
+	int bpp;
+	unsigned int i, target_mbps, mpclk;
+	unsigned long pllref;
+
+	bpp = mipi_dsi_pixel_format_to_bpp(format);
+	if (bpp < 0) {
+		DRM_DEV_ERROR(dsi->dev, "failed to get bpp for format %d: %d\n",
+			      format, bpp);
+		return bpp;
+	}
+
+	pllref = clk_get_rate(dsi->pllref_clk);
+	if (pllref != 27000000)
+		DRM_WARN("DSI pllref_clk not set to 27Mhz\n");
+
+	mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
+	if (mpclk) {
+		/* take 1/0.7 blanking overhead into consideration */
+		target_mbps = (mpclk * (bpp / lanes) * 10) / 7;
+	} else {
+		DRM_DEV_ERROR(dsi->dev, "use default 1Gbps DPHY pll clock\n");
+		target_mbps = 1000;
+	}
+
+	DRM_DEV_DEBUG(dsi->dev, "target pllref_clk frequency is %uMbps\n",
+		      target_mbps);
+
+	for (i = 0; i < ARRAY_SIZE(dptdin_map); i++) {
+		if (target_mbps < dptdin_map[i].max_mbps) {
+			*lane_mbps = dptdin_map[i].max_mbps;
+			dsi->lane_mbps = *lane_mbps;
+			DRM_DEV_DEBUG(dsi->dev,
+				      "real pllref_clk frequency is %uMbps\n",
+				      *lane_mbps);
+			return 0;
+		}
+	}
+
+	DRM_DEV_ERROR(dsi->dev, "DPHY clock frequency %uMbps is out of range\n",
+		      target_mbps);
+
+	return -EINVAL;
+}
+
+static int
+dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
+			   struct dw_mipi_dsi_dphy_timing *timing)
+{
+	timing->clk_hs2lp = 0x40;
+	timing->clk_lp2hs = 0x40;
+	timing->data_hs2lp = 0x40;
+	timing->data_lp2hs = 0x40;
+
+	return 0;
+}
+
+static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_imx6_phy_ops = {
+	.init = imx_mipi_dsi_phy_init,
+	.get_lane_mbps = imx_mipi_dsi_get_lane_mbps,
+	.get_timing = dw_mipi_dsi_phy_get_timing,
+};
+
+static struct dw_mipi_dsi_plat_data imx6q_mipi_dsi_drv_data = {
+	.max_data_lanes = 2,
+	.mode_valid = imx_mipi_dsi_mode_valid,
+	.phy_ops = &dw_mipi_dsi_imx6_phy_ops,
+};
+
+static const struct of_device_id imx_dsi_dt_ids[] = {
+	{
+		.compatible = "fsl,imx6q-mipi-dsi",
+		.data = &imx6q_mipi_dsi_drv_data,
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_dsi_dt_ids);
+
+static int imx_mipi_dsi_bind(struct device *dev, struct device *master,
+			     void *data)
+{
+	struct imx_mipi_dsi *dsi = dev_get_drvdata(dev);
+	struct drm_device *drm = data;
+	int ret;
+
+	ret = clk_prepare_enable(dsi->pllref_clk);
+	if (ret) {
+		DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
+		return ret;
+	}
+
+	ret = imx_mipi_dsi_register(drm, dsi);
+	if (ret) {
+		DRM_DEV_ERROR(dev, "Failed to register: %d\n", ret);
+		return ret;
+	}
+
+	ret = dw_mipi_dsi_bind(dsi->mipi_dsi, &dsi->encoder);
+	if (ret) {
+		DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void imx_mipi_dsi_unbind(struct device *dev, struct device *master,
+				void *data)
+{
+	struct imx_mipi_dsi *dsi = dev_get_drvdata(dev);
+
+	dw_mipi_dsi_unbind(dsi->mipi_dsi);
+
+	clk_disable_unprepare(dsi->pllref_clk);
+}
+
+static const struct component_ops imx_mipi_dsi_ops = {
+	.bind	= imx_mipi_dsi_bind,
+	.unbind	= imx_mipi_dsi_unbind,
+};
+
+static int imx_mipi_dsi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	const struct of_device_id *of_id = of_match_device(imx_dsi_dt_ids, dev);
+	struct dw_mipi_dsi_plat_data *pdata = (struct dw_mipi_dsi_plat_data *) of_id->data;
+	struct imx_mipi_dsi *dsi;
+	struct resource *res;
+	int ret;
+
+	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
+	if (!dsi)
+		return -ENOMEM;
+
+	dsi->dev = dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dsi->base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(dsi->base)) {
+		ret = PTR_ERR(dsi->base);
+		DRM_DEV_ERROR(dev, "Unable to get dsi registers: %d\n", ret);
+		return ret;
+	}
+
+	dsi->pllref_clk = devm_clk_get(dev, "ref");
+	if (IS_ERR(dsi->pllref_clk)) {
+		ret = PTR_ERR(dsi->pllref_clk);
+		DRM_DEV_ERROR(dev, "Unable to get pllref_clk: %d\n", ret);
+		return ret;
+	}
+
+	dsi->mux_sel = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr");
+	if (IS_ERR(dsi->mux_sel)) {
+		ret = PTR_ERR(dsi->mux_sel);
+		DRM_DEV_ERROR(dev, "Failed to get GPR regmap: %d\n", ret);
+		return ret;
+	}
+
+	dev_set_drvdata(dev, dsi);
+
+	imx6q_mipi_dsi_drv_data.base = dsi->base;
+	imx6q_mipi_dsi_drv_data.priv_data = dsi;
+
+	dsi->mipi_dsi = dw_mipi_dsi_probe(pdev, pdata);
+	if (IS_ERR(dsi->mipi_dsi)) {
+		ret = PTR_ERR(dsi->mipi_dsi);
+		DRM_DEV_ERROR(dev, "Failed to probe DW DSI host: %d\n", ret);
+		goto err_clkdisable;
+	}
+
+	return component_add(&pdev->dev, &imx_mipi_dsi_ops);
+
+err_clkdisable:
+	clk_disable_unprepare(dsi->pllref_clk);
+	return ret;
+}
+
+static int imx_mipi_dsi_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &imx_mipi_dsi_ops);
+	return 0;
+}
+
+static struct platform_driver imx_mipi_dsi_driver = {
+	.probe		= imx_mipi_dsi_probe,
+	.remove		= imx_mipi_dsi_remove,
+	.driver		= {
+		.of_match_table = imx_dsi_dt_ids,
+		.name	= "dw-mipi-dsi-imx6",
+	},
+};
+module_platform_driver(imx_mipi_dsi_driver);
+
+MODULE_DESCRIPTION("i.MX6 MIPI DSI host controller driver");
+MODULE_AUTHOR("Liu Ying <victor.liu-3arQi8VN3Tc@public.gmane.org>");
+MODULE_AUTHOR("Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>");
+MODULE_LICENSE("GPL");
-- 
2.26.0

Re: [PATCH v6 4/8] drm: imx: Add i.MX 6 MIPI DSI host platform driver

[Enric Balletbo Serra]

Hi Adrian,

Thank you for your patch.

Missatge de Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> del dia dt., 14
d’abr. 2020 a les 17:19:
>
> This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
> controller which is embedded in i.MX 6 SoCs.
>
> Based on following patches, but updated/extended to work with existing
> support found in the kernel:
>
> - drm: imx: Support Synopsys DesignWare MIPI DSI host controller
>   Signed-off-by: Liu Ying <Ying.Liu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
>
> Cc: Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Reviewed-by: Emil Velikov <emil.velikov-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Tested-by: Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Signed-off-by: Sjoerd Simons <sjoerd.simons-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Signed-off-by: Martyn Welch <martyn.welch-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Signed-off-by: Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> ---
> Changes since v5:
>   - Reword to remove unrelated device tree patch mention (Fabio)
>   - Move pllref_clk enable/disable to bind/unbind (Ezequiel)
>   - Fix freescale.com -> nxp.com email addresses (Fabio)
>   - Also added myself as module author (Fabio)
>   - Use DRM_DEV_* macros for consistency, print more error msg
>
> Changes since v4:
>   - Split off driver-specific configuration of phy timings due
>   to new upstream API.
>   - Move regmap infrastructure logic to separate commit (Ezequiel)
>   - Move dsi v1.01 layout addition to a separate commit (Ezequiel)
>   - Minor warnings and driver name fixes
>
> Changes since v3:
>   - Renamed platform driver to reflect it's i.MX6 only. (Fabio)
>
> Changes since v2:
>   - Fixed commit tags. (Emil)
>
> Changes since v1:
>   - Moved register definitions & regmap initialization into bridge
>   module. Platform drivers get the regmap via plat_data after
>   calling the bridge probe. (Emil)
> ---
>  drivers/gpu/drm/imx/Kconfig            |   7 +
>  drivers/gpu/drm/imx/Makefile           |   1 +
>  drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 409 +++++++++++++++++++++++++
>  3 files changed, 417 insertions(+)
>  create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
>
> diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
> index 207bf7409dfb..b49e70e7f0fd 100644
> --- a/drivers/gpu/drm/imx/Kconfig
> +++ b/drivers/gpu/drm/imx/Kconfig
> @@ -39,3 +39,10 @@ config DRM_IMX_HDMI
>         depends on DRM_IMX
>         help
>           Choose this if you want to use HDMI on i.MX6.
> +
> +config DRM_IMX6_MIPI_DSI
> +       tristate "Freescale i.MX6 DRM MIPI DSI"
> +       select DRM_DW_MIPI_DSI
> +       depends on DRM_IMX

Should it depend on CONFIG_OF too? I suspect you'll get build errors
if OF is not selected

> +       help
> +         Choose this if you want to use MIPI DSI on i.MX6.
> diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
> index 21cdcc2faabc..9a7843c59347 100644
> --- a/drivers/gpu/drm/imx/Makefile
> +++ b/drivers/gpu/drm/imx/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
>  obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
>
>  obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
> +obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o
> diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
> new file mode 100644
> index 000000000000..6914db8ce8cb
> --- /dev/null
> +++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
> @@ -0,0 +1,409 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * i.MX6 drm driver - MIPI DSI Host Controller
> + *
> + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
> + * Copyright (C) 2019-2020 Collabora, Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +#include <linux/videodev2.h>
> +#include <drm/bridge/dw_mipi_dsi.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_print.h>
> +
> +#include "imx-drm.h"
> +
> +#define DSI_PWR_UP                     0x04
> +#define RESET                          0
> +#define POWERUP                                BIT(0)
> +
> +#define DSI_PHY_IF_CTRL                        0x5c
> +#define PHY_IF_CTRL_RESET              0x0
> +
> +#define DSI_PHY_TST_CTRL0              0x64
> +#define PHY_TESTCLK                    BIT(1)
> +#define PHY_UNTESTCLK                  0
> +#define PHY_TESTCLR                    BIT(0)
> +#define PHY_UNTESTCLR                  0
> +
> +#define DSI_PHY_TST_CTRL1              0x68
> +#define PHY_TESTEN                     BIT(16)
> +#define PHY_UNTESTEN                   0
> +#define PHY_TESTDOUT(n)                        (((n) & 0xff) << 8)
> +#define PHY_TESTDIN(n)                 (((n) & 0xff) << 0)
> +
> +struct imx_mipi_dsi {
> +       struct drm_encoder encoder;
> +       struct device *dev;
> +       struct regmap *mux_sel;
> +       struct dw_mipi_dsi *mipi_dsi;
> +       struct clk *pllref_clk;
> +
> +       void __iomem *base;
> +       unsigned int lane_mbps;
> +};
> +
> +struct dphy_pll_testdin_map {
> +       unsigned int max_mbps;
> +       u8 testdin;
> +};
> +
> +/* The table is based on 27MHz DPHY pll reference clock. */
> +static const struct dphy_pll_testdin_map dptdin_map[] = {
> +       {160, 0x04}, {180, 0x24}, {200, 0x44}, {210, 0x06},
> +       {240, 0x26}, {250, 0x46}, {270, 0x08}, {300, 0x28},
> +       {330, 0x48}, {360, 0x2a}, {400, 0x4a}, {450, 0x0c},
> +       {500, 0x2c}, {550, 0x0e}, {600, 0x2e}, {650, 0x10},
> +       {700, 0x30}, {750, 0x12}, {800, 0x32}, {850, 0x14},
> +       {900, 0x34}, {950, 0x54}, {1000, 0x74}
> +};
> +
> +static inline struct imx_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
> +{
> +       return container_of(enc, struct imx_mipi_dsi, encoder);
> +}
> +
> +static void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, int ipu_di)
> +{
> +       regmap_update_bits(dsi->mux_sel, IOMUXC_GPR3,
> +                          IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
> +                          ipu_di << IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT);
> +}
> +
> +static const struct drm_encoder_funcs imx_mipi_dsi_encoder_funcs = {
> +       .destroy = imx_drm_encoder_destroy,
> +};
> +
> +static bool imx_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
> +                                           const struct drm_display_mode *mode,
> +                                           struct drm_display_mode *adj_mode)
> +{
> +       return true;
> +}
> +
> +static int imx_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> +                                            struct drm_crtc_state *crtc_state,
> +                                            struct drm_connector_state *conn)
> +{
> +       struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
> +
> +       /* The following values are taken from dw_hdmi_imx_atomic_check */
> +       imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
> +       imx_crtc_state->di_hsync_pin = 2;
> +       imx_crtc_state->di_vsync_pin = 3;
> +
> +       return 0;
> +}
> +
> +static void imx_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
> +{
> +       struct imx_mipi_dsi *dsi = enc_to_dsi(encoder);
> +       int mux = drm_of_encoder_active_port_id(dsi->dev->of_node, encoder);
> +
> +       imx_mipi_dsi_set_ipu_di_mux(dsi, mux);
> +}
> +
> +static void imx_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
> +{
> +}
> +
> +static const struct drm_encoder_helper_funcs imx_mipi_dsi_encoder_helpers = {

AFAIK (or at least this is the feedback I received) drm_encoder is
kind of deprecated, and nowadays all is migrated to drm_bridge
(encoders, bridges and panels). Of course, a drm_encoder is needed, as
the DRM core expects one, but should just be a dummy object that you
can probably create with just calling  drm_simple_encoder_init(). DRM
maintainers, please shout if I am wrong.

> +       .mode_fixup = imx_mipi_dsi_encoder_mode_fixup,
> +       .commit = imx_mipi_dsi_encoder_commit,
> +       .disable = imx_mipi_dsi_encoder_disable,
> +       .atomic_check = imx_mipi_dsi_encoder_atomic_check,
> +};
> +
> +static int imx_mipi_dsi_register(struct drm_device *drm,
> +                                struct imx_mipi_dsi *dsi)
> +{
> +       int ret;
> +
> +       ret = imx_drm_encoder_parse_of(drm, &dsi->encoder, dsi->dev->of_node);
> +       if (ret)
> +               return ret;
> +
> +       drm_encoder_helper_add(&dsi->encoder,
> +                              &imx_mipi_dsi_encoder_helpers);
> +       drm_encoder_init(drm, &dsi->encoder, &imx_mipi_dsi_encoder_funcs,
> +                        DRM_MODE_ENCODER_DSI, NULL);
> +       return 0;
> +}
> +
> +static enum drm_mode_status imx_mipi_dsi_mode_valid(void *priv_data,
> +                                       const struct drm_display_mode *mode)
> +{
> +       /*
> +        * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG
> +        * register is 11-bit.
> +        */
> +       if (mode->hdisplay > 0x7ff)
> +               return MODE_BAD_HVALUE;
> +
> +       /*
> +        * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG
> +        * register is 11-bit.
> +        */
> +       if (mode->vdisplay > 0x7ff)
> +               return MODE_BAD_VVALUE;
> +
> +       return MODE_OK;
> +}
> +
> +
> +static unsigned int max_mbps_to_testdin(unsigned int max_mbps)
> +{
> +       unsigned int i;
> +
> +       for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
> +               if (dptdin_map[i].max_mbps == max_mbps)
> +                       return dptdin_map[i].testdin;
> +
> +       return -EINVAL;
> +}
> +
> +static inline void dsi_write(struct imx_mipi_dsi *dsi, u32 reg, u32 val)
> +{
> +       writel(val, dsi->base + reg);
> +}
> +
> +static int imx_mipi_dsi_phy_init(void *priv_data)
> +{
> +       struct imx_mipi_dsi *dsi = priv_data;
> +       int testdin;
> +
> +       testdin = max_mbps_to_testdin(dsi->lane_mbps);
> +       if (testdin < 0) {
> +               DRM_DEV_ERROR(dsi->dev,
> +                             "failed to get testdin for %dmbps lane clock\n",
> +                             dsi->lane_mbps);
> +               return testdin;
> +       }
> +
> +       dsi_write(dsi, DSI_PHY_IF_CTRL, PHY_IF_CTRL_RESET);
> +       dsi_write(dsi, DSI_PWR_UP, POWERUP);
> +
> +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
> +       dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
> +                 PHY_TESTDIN(0x44));
> +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
> +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
> +       dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
> +                 PHY_TESTDIN(testdin));
> +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
> +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
> +
> +       return 0;
> +}
> +
> +static int imx_mipi_dsi_get_lane_mbps(void *priv_data,
> +                                     const struct drm_display_mode *mode,
> +                                     unsigned long mode_flags, u32 lanes,
> +                                     u32 format, unsigned int *lane_mbps)
> +{
> +       struct imx_mipi_dsi *dsi = priv_data;
> +       int bpp;
> +       unsigned int i, target_mbps, mpclk;
> +       unsigned long pllref;
> +
> +       bpp = mipi_dsi_pixel_format_to_bpp(format);
> +       if (bpp < 0) {
> +               DRM_DEV_ERROR(dsi->dev, "failed to get bpp for format %d: %d\n",
> +                             format, bpp);
> +               return bpp;
> +       }
> +
> +       pllref = clk_get_rate(dsi->pllref_clk);
> +       if (pllref != 27000000)
> +               DRM_WARN("DSI pllref_clk not set to 27Mhz\n");
> +
> +       mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
> +       if (mpclk) {
> +               /* take 1/0.7 blanking overhead into consideration */
> +               target_mbps = (mpclk * (bpp / lanes) * 10) / 7;
> +       } else {
> +               DRM_DEV_ERROR(dsi->dev, "use default 1Gbps DPHY pll clock\n");
> +               target_mbps = 1000;
> +       }
> +
> +       DRM_DEV_DEBUG(dsi->dev, "target pllref_clk frequency is %uMbps\n",
> +                     target_mbps);
> +
> +       for (i = 0; i < ARRAY_SIZE(dptdin_map); i++) {
> +               if (target_mbps < dptdin_map[i].max_mbps) {
> +                       *lane_mbps = dptdin_map[i].max_mbps;
> +                       dsi->lane_mbps = *lane_mbps;
> +                       DRM_DEV_DEBUG(dsi->dev,
> +                                     "real pllref_clk frequency is %uMbps\n",
> +                                     *lane_mbps);
> +                       return 0;
> +               }
> +       }
> +
> +       DRM_DEV_ERROR(dsi->dev, "DPHY clock frequency %uMbps is out of range\n",
> +                     target_mbps);
> +
> +       return -EINVAL;
> +}
> +
> +static int
> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> +                          struct dw_mipi_dsi_dphy_timing *timing)
> +{
> +       timing->clk_hs2lp = 0x40;
> +       timing->clk_lp2hs = 0x40;
> +       timing->data_hs2lp = 0x40;
> +       timing->data_lp2hs = 0x40;
> +
> +       return 0;
> +}
> +
> +static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_imx6_phy_ops = {
> +       .init = imx_mipi_dsi_phy_init,
> +       .get_lane_mbps = imx_mipi_dsi_get_lane_mbps,
> +       .get_timing = dw_mipi_dsi_phy_get_timing,
> +};
> +
> +static struct dw_mipi_dsi_plat_data imx6q_mipi_dsi_drv_data = {
> +       .max_data_lanes = 2,
> +       .mode_valid = imx_mipi_dsi_mode_valid,
> +       .phy_ops = &dw_mipi_dsi_imx6_phy_ops,
> +};
> +
> +static const struct of_device_id imx_dsi_dt_ids[] = {
> +       {
> +               .compatible = "fsl,imx6q-mipi-dsi",
> +               .data = &imx6q_mipi_dsi_drv_data,
> +       },
> +       { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, imx_dsi_dt_ids);
> +
> +static int imx_mipi_dsi_bind(struct device *dev, struct device *master,
> +                            void *data)
> +{
> +       struct imx_mipi_dsi *dsi = dev_get_drvdata(dev);
> +       struct drm_device *drm = data;
> +       int ret;
> +
> +       ret = clk_prepare_enable(dsi->pllref_clk);
> +       if (ret) {
> +               DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
> +               return ret;
> +       }
> +
> +       ret = imx_mipi_dsi_register(drm, dsi);
> +       if (ret) {
> +               DRM_DEV_ERROR(dev, "Failed to register: %d\n", ret);
> +               return ret;
> +       }
> +
> +       ret = dw_mipi_dsi_bind(dsi->mipi_dsi, &dsi->encoder);
> +       if (ret) {
> +               DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static void imx_mipi_dsi_unbind(struct device *dev, struct device *master,
> +                               void *data)
> +{
> +       struct imx_mipi_dsi *dsi = dev_get_drvdata(dev);
> +
> +       dw_mipi_dsi_unbind(dsi->mipi_dsi);
> +
> +       clk_disable_unprepare(dsi->pllref_clk);
> +}
> +
> +static const struct component_ops imx_mipi_dsi_ops = {
> +       .bind   = imx_mipi_dsi_bind,
> +       .unbind = imx_mipi_dsi_unbind,
> +};
> +
> +static int imx_mipi_dsi_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       const struct of_device_id *of_id = of_match_device(imx_dsi_dt_ids, dev);
> +       struct dw_mipi_dsi_plat_data *pdata = (struct dw_mipi_dsi_plat_data *) of_id->data;
> +       struct imx_mipi_dsi *dsi;
> +       struct resource *res;
> +       int ret;
> +
> +       dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> +       if (!dsi)
> +               return -ENOMEM;
> +
> +       dsi->dev = dev;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       dsi->base = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(dsi->base)) {
> +               ret = PTR_ERR(dsi->base);
> +               DRM_DEV_ERROR(dev, "Unable to get dsi registers: %d\n", ret);
> +               return ret;
> +       }
> +
> +       dsi->pllref_clk = devm_clk_get(dev, "ref");
> +       if (IS_ERR(dsi->pllref_clk)) {
> +               ret = PTR_ERR(dsi->pllref_clk);
> +               DRM_DEV_ERROR(dev, "Unable to get pllref_clk: %d\n", ret);
> +               return ret;
> +       }
> +
> +       dsi->mux_sel = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr");
> +       if (IS_ERR(dsi->mux_sel)) {
> +               ret = PTR_ERR(dsi->mux_sel);
> +               DRM_DEV_ERROR(dev, "Failed to get GPR regmap: %d\n", ret);
> +               return ret;
> +       }
> +
> +       dev_set_drvdata(dev, dsi);
> +
> +       imx6q_mipi_dsi_drv_data.base = dsi->base;
> +       imx6q_mipi_dsi_drv_data.priv_data = dsi;
> +
> +       dsi->mipi_dsi = dw_mipi_dsi_probe(pdev, pdata);
> +       if (IS_ERR(dsi->mipi_dsi)) {
> +               ret = PTR_ERR(dsi->mipi_dsi);
> +               DRM_DEV_ERROR(dev, "Failed to probe DW DSI host: %d\n", ret);
> +               goto err_clkdisable;
> +       }
> +
> +       return component_add(&pdev->dev, &imx_mipi_dsi_ops);
> +
> +err_clkdisable:
> +       clk_disable_unprepare(dsi->pllref_clk);
> +       return ret;
> +}
> +
> +static int imx_mipi_dsi_remove(struct platform_device *pdev)
> +{
> +       component_del(&pdev->dev, &imx_mipi_dsi_ops);
> +       return 0;
> +}
> +
> +static struct platform_driver imx_mipi_dsi_driver = {
> +       .probe          = imx_mipi_dsi_probe,
> +       .remove         = imx_mipi_dsi_remove,
> +       .driver         = {
> +               .of_match_table = imx_dsi_dt_ids,
> +               .name   = "dw-mipi-dsi-imx6",
> +       },
> +};
> +module_platform_driver(imx_mipi_dsi_driver);
> +
> +MODULE_DESCRIPTION("i.MX6 MIPI DSI host controller driver");
> +MODULE_AUTHOR("Liu Ying <victor.liu-3arQi8VN3Tc@public.gmane.org>");
> +MODULE_AUTHOR("Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>");
> +MODULE_LICENSE("GPL");
> --
> 2.26.0
>
> _______________________________________________
> dri-devel mailing list
> dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH v6 4/8] drm: imx: Add i.MX 6 MIPI DSI host platform driver

[Laurent Pinchart]

Hi Enric,

On Wed, Apr 15, 2020 at 07:26:02PM +0200, Enric Balletbo Serra wrote:
> Missatge de Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> del dia dt., 14
> d’abr. 2020 a les 17:19:
> >
> > This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
> > controller which is embedded in i.MX 6 SoCs.
> >
> > Based on following patches, but updated/extended to work with existing
> > support found in the kernel:
> >
> > - drm: imx: Support Synopsys DesignWare MIPI DSI host controller
> >   Signed-off-by: Liu Ying <Ying.Liu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> >
> > Cc: Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > Reviewed-by: Emil Velikov <emil.velikov-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> > Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > Tested-by: Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> > Signed-off-by: Sjoerd Simons <sjoerd.simons-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> > Signed-off-by: Martyn Welch <martyn.welch-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> > Signed-off-by: Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> > ---
> > Changes since v5:
> >   - Reword to remove unrelated device tree patch mention (Fabio)
> >   - Move pllref_clk enable/disable to bind/unbind (Ezequiel)
> >   - Fix freescale.com -> nxp.com email addresses (Fabio)
> >   - Also added myself as module author (Fabio)
> >   - Use DRM_DEV_* macros for consistency, print more error msg
> >
> > Changes since v4:
> >   - Split off driver-specific configuration of phy timings due
> >   to new upstream API.
> >   - Move regmap infrastructure logic to separate commit (Ezequiel)
> >   - Move dsi v1.01 layout addition to a separate commit (Ezequiel)
> >   - Minor warnings and driver name fixes
> >
> > Changes since v3:
> >   - Renamed platform driver to reflect it's i.MX6 only. (Fabio)
> >
> > Changes since v2:
> >   - Fixed commit tags. (Emil)
> >
> > Changes since v1:
> >   - Moved register definitions & regmap initialization into bridge
> >   module. Platform drivers get the regmap via plat_data after
> >   calling the bridge probe. (Emil)
> > ---
> >  drivers/gpu/drm/imx/Kconfig            |   7 +
> >  drivers/gpu/drm/imx/Makefile           |   1 +
> >  drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 409 +++++++++++++++++++++++++
> >  3 files changed, 417 insertions(+)
> >  create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
> >
> > diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
> > index 207bf7409dfb..b49e70e7f0fd 100644
> > --- a/drivers/gpu/drm/imx/Kconfig
> > +++ b/drivers/gpu/drm/imx/Kconfig
> > @@ -39,3 +39,10 @@ config DRM_IMX_HDMI
> >         depends on DRM_IMX
> >         help
> >           Choose this if you want to use HDMI on i.MX6.
> > +
> > +config DRM_IMX6_MIPI_DSI
> > +       tristate "Freescale i.MX6 DRM MIPI DSI"
> > +       select DRM_DW_MIPI_DSI
> > +       depends on DRM_IMX
> 
> Should it depend on CONFIG_OF too? I suspect you'll get build errors
> if OF is not selected
> 
> > +       help
> > +         Choose this if you want to use MIPI DSI on i.MX6.
> > diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
> > index 21cdcc2faabc..9a7843c59347 100644
> > --- a/drivers/gpu/drm/imx/Makefile
> > +++ b/drivers/gpu/drm/imx/Makefile
> > @@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
> >  obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
> >
> >  obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
> > +obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o
> > diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
> > new file mode 100644
> > index 000000000000..6914db8ce8cb
> > --- /dev/null
> > +++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
> > @@ -0,0 +1,409 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * i.MX6 drm driver - MIPI DSI Host Controller
> > + *
> > + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
> > + * Copyright (C) 2019-2020 Collabora, Ltd.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/regmap.h>
> > +#include <linux/videodev2.h>
> > +#include <drm/bridge/dw_mipi_dsi.h>
> > +#include <drm/drm_crtc_helper.h>
> > +#include <drm/drm_mipi_dsi.h>
> > +#include <drm/drm_of.h>
> > +#include <drm/drm_print.h>
> > +
> > +#include "imx-drm.h"
> > +
> > +#define DSI_PWR_UP                     0x04
> > +#define RESET                          0
> > +#define POWERUP                                BIT(0)
> > +
> > +#define DSI_PHY_IF_CTRL                        0x5c
> > +#define PHY_IF_CTRL_RESET              0x0
> > +
> > +#define DSI_PHY_TST_CTRL0              0x64
> > +#define PHY_TESTCLK                    BIT(1)
> > +#define PHY_UNTESTCLK                  0
> > +#define PHY_TESTCLR                    BIT(0)
> > +#define PHY_UNTESTCLR                  0
> > +
> > +#define DSI_PHY_TST_CTRL1              0x68
> > +#define PHY_TESTEN                     BIT(16)
> > +#define PHY_UNTESTEN                   0
> > +#define PHY_TESTDOUT(n)                        (((n) & 0xff) << 8)
> > +#define PHY_TESTDIN(n)                 (((n) & 0xff) << 0)
> > +
> > +struct imx_mipi_dsi {
> > +       struct drm_encoder encoder;
> > +       struct device *dev;
> > +       struct regmap *mux_sel;
> > +       struct dw_mipi_dsi *mipi_dsi;
> > +       struct clk *pllref_clk;
> > +
> > +       void __iomem *base;
> > +       unsigned int lane_mbps;
> > +};
> > +
> > +struct dphy_pll_testdin_map {
> > +       unsigned int max_mbps;
> > +       u8 testdin;
> > +};
> > +
> > +/* The table is based on 27MHz DPHY pll reference clock. */
> > +static const struct dphy_pll_testdin_map dptdin_map[] = {
> > +       {160, 0x04}, {180, 0x24}, {200, 0x44}, {210, 0x06},
> > +       {240, 0x26}, {250, 0x46}, {270, 0x08}, {300, 0x28},
> > +       {330, 0x48}, {360, 0x2a}, {400, 0x4a}, {450, 0x0c},
> > +       {500, 0x2c}, {550, 0x0e}, {600, 0x2e}, {650, 0x10},
> > +       {700, 0x30}, {750, 0x12}, {800, 0x32}, {850, 0x14},
> > +       {900, 0x34}, {950, 0x54}, {1000, 0x74}
> > +};
> > +
> > +static inline struct imx_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
> > +{
> > +       return container_of(enc, struct imx_mipi_dsi, encoder);
> > +}
> > +
> > +static void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, int ipu_di)
> > +{
> > +       regmap_update_bits(dsi->mux_sel, IOMUXC_GPR3,
> > +                          IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
> > +                          ipu_di << IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT);
> > +}
> > +
> > +static const struct drm_encoder_funcs imx_mipi_dsi_encoder_funcs = {
> > +       .destroy = imx_drm_encoder_destroy,
> > +};
> > +
> > +static bool imx_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
> > +                                           const struct drm_display_mode *mode,
> > +                                           struct drm_display_mode *adj_mode)
> > +{
> > +       return true;
> > +}
> > +
> > +static int imx_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> > +                                            struct drm_crtc_state *crtc_state,
> > +                                            struct drm_connector_state *conn)
> > +{
> > +       struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
> > +
> > +       /* The following values are taken from dw_hdmi_imx_atomic_check */
> > +       imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
> > +       imx_crtc_state->di_hsync_pin = 2;
> > +       imx_crtc_state->di_vsync_pin = 3;
> > +
> > +       return 0;
> > +}
> > +
> > +static void imx_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
> > +{
> > +       struct imx_mipi_dsi *dsi = enc_to_dsi(encoder);
> > +       int mux = drm_of_encoder_active_port_id(dsi->dev->of_node, encoder);
> > +
> > +       imx_mipi_dsi_set_ipu_di_mux(dsi, mux);
> > +}
> > +
> > +static void imx_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
> > +{
> > +}
> > +
> > +static const struct drm_encoder_helper_funcs imx_mipi_dsi_encoder_helpers = {
> 
> AFAIK (or at least this is the feedback I received) drm_encoder is
> kind of deprecated, and nowadays all is migrated to drm_bridge
> (encoders, bridges and panels). Of course, a drm_encoder is needed, as
> the DRM core expects one, but should just be a dummy object that you
> can probably create with just calling  drm_simple_encoder_init(). DRM
> maintainers, please shout if I am wrong.

That certainly matches my position :-) I would also add that the DRM
encoder should be created in imx-drm-core.c or in ipuv3-crtc.c, not
here.

> > +       .mode_fixup = imx_mipi_dsi_encoder_mode_fixup,
> > +       .commit = imx_mipi_dsi_encoder_commit,
> > +       .disable = imx_mipi_dsi_encoder_disable,
> > +       .atomic_check = imx_mipi_dsi_encoder_atomic_check,
> > +};
> > +
> > +static int imx_mipi_dsi_register(struct drm_device *drm,
> > +                                struct imx_mipi_dsi *dsi)
> > +{
> > +       int ret;
> > +
> > +       ret = imx_drm_encoder_parse_of(drm, &dsi->encoder, dsi->dev->of_node);
> > +       if (ret)
> > +               return ret;
> > +
> > +       drm_encoder_helper_add(&dsi->encoder,
> > +                              &imx_mipi_dsi_encoder_helpers);
> > +       drm_encoder_init(drm, &dsi->encoder, &imx_mipi_dsi_encoder_funcs,
> > +                        DRM_MODE_ENCODER_DSI, NULL);
> > +       return 0;
> > +}
> > +
> > +static enum drm_mode_status imx_mipi_dsi_mode_valid(void *priv_data,
> > +                                       const struct drm_display_mode *mode)
> > +{
> > +       /*
> > +        * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG
> > +        * register is 11-bit.
> > +        */
> > +       if (mode->hdisplay > 0x7ff)
> > +               return MODE_BAD_HVALUE;
> > +
> > +       /*
> > +        * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG
> > +        * register is 11-bit.
> > +        */
> > +       if (mode->vdisplay > 0x7ff)
> > +               return MODE_BAD_VVALUE;
> > +
> > +       return MODE_OK;
> > +}
> > +
> > +
> > +static unsigned int max_mbps_to_testdin(unsigned int max_mbps)
> > +{
> > +       unsigned int i;
> > +
> > +       for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
> > +               if (dptdin_map[i].max_mbps == max_mbps)
> > +                       return dptdin_map[i].testdin;
> > +
> > +       return -EINVAL;
> > +}
> > +
> > +static inline void dsi_write(struct imx_mipi_dsi *dsi, u32 reg, u32 val)
> > +{
> > +       writel(val, dsi->base + reg);
> > +}
> > +
> > +static int imx_mipi_dsi_phy_init(void *priv_data)
> > +{
> > +       struct imx_mipi_dsi *dsi = priv_data;
> > +       int testdin;
> > +
> > +       testdin = max_mbps_to_testdin(dsi->lane_mbps);
> > +       if (testdin < 0) {
> > +               DRM_DEV_ERROR(dsi->dev,
> > +                             "failed to get testdin for %dmbps lane clock\n",
> > +                             dsi->lane_mbps);
> > +               return testdin;
> > +       }
> > +
> > +       dsi_write(dsi, DSI_PHY_IF_CTRL, PHY_IF_CTRL_RESET);
> > +       dsi_write(dsi, DSI_PWR_UP, POWERUP);
> > +
> > +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
> > +       dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
> > +                 PHY_TESTDIN(0x44));
> > +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
> > +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
> > +       dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
> > +                 PHY_TESTDIN(testdin));
> > +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
> > +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
> > +
> > +       return 0;
> > +}
> > +
> > +static int imx_mipi_dsi_get_lane_mbps(void *priv_data,
> > +                                     const struct drm_display_mode *mode,
> > +                                     unsigned long mode_flags, u32 lanes,
> > +                                     u32 format, unsigned int *lane_mbps)
> > +{
> > +       struct imx_mipi_dsi *dsi = priv_data;
> > +       int bpp;
> > +       unsigned int i, target_mbps, mpclk;
> > +       unsigned long pllref;
> > +
> > +       bpp = mipi_dsi_pixel_format_to_bpp(format);
> > +       if (bpp < 0) {
> > +               DRM_DEV_ERROR(dsi->dev, "failed to get bpp for format %d: %d\n",
> > +                             format, bpp);
> > +               return bpp;
> > +       }
> > +
> > +       pllref = clk_get_rate(dsi->pllref_clk);
> > +       if (pllref != 27000000)
> > +               DRM_WARN("DSI pllref_clk not set to 27Mhz\n");
> > +
> > +       mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
> > +       if (mpclk) {
> > +               /* take 1/0.7 blanking overhead into consideration */
> > +               target_mbps = (mpclk * (bpp / lanes) * 10) / 7;
> > +       } else {
> > +               DRM_DEV_ERROR(dsi->dev, "use default 1Gbps DPHY pll clock\n");
> > +               target_mbps = 1000;
> > +       }
> > +
> > +       DRM_DEV_DEBUG(dsi->dev, "target pllref_clk frequency is %uMbps\n",
> > +                     target_mbps);
> > +
> > +       for (i = 0; i < ARRAY_SIZE(dptdin_map); i++) {
> > +               if (target_mbps < dptdin_map[i].max_mbps) {
> > +                       *lane_mbps = dptdin_map[i].max_mbps;
> > +                       dsi->lane_mbps = *lane_mbps;
> > +                       DRM_DEV_DEBUG(dsi->dev,
> > +                                     "real pllref_clk frequency is %uMbps\n",
> > +                                     *lane_mbps);
> > +                       return 0;
> > +               }
> > +       }
> > +
> > +       DRM_DEV_ERROR(dsi->dev, "DPHY clock frequency %uMbps is out of range\n",
> > +                     target_mbps);
> > +
> > +       return -EINVAL;
> > +}
> > +
> > +static int
> > +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> > +                          struct dw_mipi_dsi_dphy_timing *timing)
> > +{
> > +       timing->clk_hs2lp = 0x40;
> > +       timing->clk_lp2hs = 0x40;
> > +       timing->data_hs2lp = 0x40;
> > +       timing->data_lp2hs = 0x40;
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_imx6_phy_ops = {
> > +       .init = imx_mipi_dsi_phy_init,
> > +       .get_lane_mbps = imx_mipi_dsi_get_lane_mbps,
> > +       .get_timing = dw_mipi_dsi_phy_get_timing,
> > +};
> > +
> > +static struct dw_mipi_dsi_plat_data imx6q_mipi_dsi_drv_data = {
> > +       .max_data_lanes = 2,
> > +       .mode_valid = imx_mipi_dsi_mode_valid,
> > +       .phy_ops = &dw_mipi_dsi_imx6_phy_ops,
> > +};
> > +
> > +static const struct of_device_id imx_dsi_dt_ids[] = {
> > +       {
> > +               .compatible = "fsl,imx6q-mipi-dsi",
> > +               .data = &imx6q_mipi_dsi_drv_data,
> > +       },
> > +       { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, imx_dsi_dt_ids);
> > +
> > +static int imx_mipi_dsi_bind(struct device *dev, struct device *master,
> > +                            void *data)
> > +{
> > +       struct imx_mipi_dsi *dsi = dev_get_drvdata(dev);
> > +       struct drm_device *drm = data;
> > +       int ret;
> > +
> > +       ret = clk_prepare_enable(dsi->pllref_clk);
> > +       if (ret) {
> > +               DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
> > +               return ret;
> > +       }
> > +
> > +       ret = imx_mipi_dsi_register(drm, dsi);
> > +       if (ret) {
> > +               DRM_DEV_ERROR(dev, "Failed to register: %d\n", ret);
> > +               return ret;
> > +       }
> > +
> > +       ret = dw_mipi_dsi_bind(dsi->mipi_dsi, &dsi->encoder);
> > +       if (ret) {
> > +               DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
> > +               return ret;
> > +       }
> > +
> > +       return 0;
> > +}
> > +
> > +static void imx_mipi_dsi_unbind(struct device *dev, struct device *master,
> > +                               void *data)
> > +{
> > +       struct imx_mipi_dsi *dsi = dev_get_drvdata(dev);
> > +
> > +       dw_mipi_dsi_unbind(dsi->mipi_dsi);
> > +
> > +       clk_disable_unprepare(dsi->pllref_clk);
> > +}
> > +
> > +static const struct component_ops imx_mipi_dsi_ops = {
> > +       .bind   = imx_mipi_dsi_bind,
> > +       .unbind = imx_mipi_dsi_unbind,
> > +};
> > +
> > +static int imx_mipi_dsi_probe(struct platform_device *pdev)
> > +{
> > +       struct device *dev = &pdev->dev;
> > +       const struct of_device_id *of_id = of_match_device(imx_dsi_dt_ids, dev);
> > +       struct dw_mipi_dsi_plat_data *pdata = (struct dw_mipi_dsi_plat_data *) of_id->data;
> > +       struct imx_mipi_dsi *dsi;
> > +       struct resource *res;
> > +       int ret;
> > +
> > +       dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> > +       if (!dsi)
> > +               return -ENOMEM;
> > +
> > +       dsi->dev = dev;
> > +
> > +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +       dsi->base = devm_ioremap_resource(dev, res);
> > +       if (IS_ERR(dsi->base)) {
> > +               ret = PTR_ERR(dsi->base);
> > +               DRM_DEV_ERROR(dev, "Unable to get dsi registers: %d\n", ret);
> > +               return ret;
> > +       }
> > +
> > +       dsi->pllref_clk = devm_clk_get(dev, "ref");
> > +       if (IS_ERR(dsi->pllref_clk)) {
> > +               ret = PTR_ERR(dsi->pllref_clk);
> > +               DRM_DEV_ERROR(dev, "Unable to get pllref_clk: %d\n", ret);
> > +               return ret;
> > +       }
> > +
> > +       dsi->mux_sel = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr");
> > +       if (IS_ERR(dsi->mux_sel)) {
> > +               ret = PTR_ERR(dsi->mux_sel);
> > +               DRM_DEV_ERROR(dev, "Failed to get GPR regmap: %d\n", ret);
> > +               return ret;
> > +       }
> > +
> > +       dev_set_drvdata(dev, dsi);
> > +
> > +       imx6q_mipi_dsi_drv_data.base = dsi->base;
> > +       imx6q_mipi_dsi_drv_data.priv_data = dsi;
> > +
> > +       dsi->mipi_dsi = dw_mipi_dsi_probe(pdev, pdata);
> > +       if (IS_ERR(dsi->mipi_dsi)) {
> > +               ret = PTR_ERR(dsi->mipi_dsi);
> > +               DRM_DEV_ERROR(dev, "Failed to probe DW DSI host: %d\n", ret);
> > +               goto err_clkdisable;
> > +       }
> > +
> > +       return component_add(&pdev->dev, &imx_mipi_dsi_ops);
> > +
> > +err_clkdisable:
> > +       clk_disable_unprepare(dsi->pllref_clk);
> > +       return ret;
> > +}
> > +
> > +static int imx_mipi_dsi_remove(struct platform_device *pdev)
> > +{
> > +       component_del(&pdev->dev, &imx_mipi_dsi_ops);
> > +       return 0;
> > +}
> > +
> > +static struct platform_driver imx_mipi_dsi_driver = {
> > +       .probe          = imx_mipi_dsi_probe,
> > +       .remove         = imx_mipi_dsi_remove,
> > +       .driver         = {
> > +               .of_match_table = imx_dsi_dt_ids,
> > +               .name   = "dw-mipi-dsi-imx6",
> > +       },
> > +};
> > +module_platform_driver(imx_mipi_dsi_driver);
> > +
> > +MODULE_DESCRIPTION("i.MX6 MIPI DSI host controller driver");
> > +MODULE_AUTHOR("Liu Ying <victor.liu-3arQi8VN3Tc@public.gmane.org>");
> > +MODULE_AUTHOR("Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>");
> > +MODULE_LICENSE("GPL");

-- 
Regards,

Laurent Pinchart

Re: [PATCH v6 4/8] drm: imx: Add i.MX 6 MIPI DSI host platform driver

[Adrian Ratiu]

Hi Enric & Laurent,

On Wed, 15 Apr 2020, Laurent Pinchart 
<laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org> wrote:
> Hi Enric, 
> 
> On Wed, Apr 15, 2020 at 07:26:02PM +0200, Enric Balletbo Serra 
> wrote: 
>> Missatge de Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> del dia 
>> dt., 14 d’abr. 2020 a les 17:19: 
>> > 
>> > This adds support for the Synopsis DesignWare MIPI DSI v1.01 
>> > host controller which is embedded in i.MX 6 SoCs. 
>> > 
>> > Based on following patches, but updated/extended to work with 
>> > existing support found in the kernel: 
>> > 
>> > - drm: imx: Support Synopsys DesignWare MIPI DSI host 
>> > controller 
>> >   Signed-off-by: Liu Ying <Ying.Liu-KZfg59tc24xl57MIdRCFDg@public.gmane.org> 
>> > 
>> > Cc: Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Reviewed-by: Emil 
>> > Velikov <emil.velikov-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> Tested-by: Adrian Pop 
>> > <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Tested-by: Arnaud Ferraris 
>> > <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> Signed-off-by: Sjoerd Simons 
>> > <sjoerd.simons-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> Signed-off-by: Martyn Welch 
>> > <martyn.welch-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> Signed-off-by: Adrian Ratiu 
>> > <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> --- Changes since v5: 
>> >   - Reword to remove unrelated device tree patch mention 
>> >   (Fabio) - Move pllref_clk enable/disable to bind/unbind 
>> >   (Ezequiel) - Fix freescale.com -> nxp.com email addresses 
>> >   (Fabio) - Also added myself as module author (Fabio) - Use 
>> >   DRM_DEV_* macros for consistency, print more error msg 
>> > 
>> > Changes since v4: 
>> >   - Split off driver-specific configuration of phy timings 
>> >   due to new upstream API.  - Move regmap infrastructure 
>> >   logic to separate commit (Ezequiel) - Move dsi v1.01 layout 
>> >   addition to a separate commit (Ezequiel) - Minor warnings 
>> >   and driver name fixes 
>> > 
>> > Changes since v3: 
>> >   - Renamed platform driver to reflect it's i.MX6 
>> >   only. (Fabio) 
>> > 
>> > Changes since v2: 
>> >   - Fixed commit tags. (Emil) 
>> > 
>> > Changes since v1: 
>> >   - Moved register definitions & regmap initialization into 
>> >   bridge module. Platform drivers get the regmap via 
>> >   plat_data after calling the bridge probe. (Emil) 
>> > --- 
>> >  drivers/gpu/drm/imx/Kconfig            |   7 + 
>> >  drivers/gpu/drm/imx/Makefile           |   1 + 
>> >  drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 409 
>> >  +++++++++++++++++++++++++ 3 files changed, 417 insertions(+) 
>> >  create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
>> > 
>> > diff --git a/drivers/gpu/drm/imx/Kconfig 
>> > b/drivers/gpu/drm/imx/Kconfig index 
>> > 207bf7409dfb..b49e70e7f0fd 100644 --- 
>> > a/drivers/gpu/drm/imx/Kconfig +++ 
>> > b/drivers/gpu/drm/imx/Kconfig @@ -39,3 +39,10 @@ config 
>> > DRM_IMX_HDMI 
>> >         depends on DRM_IMX help 
>> >           Choose this if you want to use HDMI on i.MX6. 
>> > + +config DRM_IMX6_MIPI_DSI +       tristate "Freescale i.MX6 
>> > DRM MIPI DSI" +       select DRM_DW_MIPI_DSI +       depends 
>> > on DRM_IMX 
>>  Should it depend on CONFIG_OF too? I suspect you'll get build 
>> errors if OF is not selected  
>> > +       help +         Choose this if you want to use MIPI 
>> > DSI on i.MX6.  diff --git a/drivers/gpu/drm/imx/Makefile 
>> > b/drivers/gpu/drm/imx/Makefile index 
>> > 21cdcc2faabc..9a7843c59347 100644 --- 
>> > a/drivers/gpu/drm/imx/Makefile +++ 
>> > b/drivers/gpu/drm/imx/Makefile @@ -9,3 +9,4 @@ 
>> > obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o 
>> >  obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o 
>> > 
>> >  obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o 
>> > +obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o diff 
>> > --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
>> > b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c new file mode 100644 
>> > index 000000000000..6914db8ce8cb --- /dev/null +++ 
>> > b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c @@ -0,0 +1,409 @@ 
>> > +// SPDX-License-Identifier: GPL-2.0+ +/* + * i.MX6 drm 
>> > driver - MIPI DSI Host Controller + * + * Copyright (C) 
>> > 2011-2015 Freescale Semiconductor, Inc.  + * Copyright (C) 
>> > 2019-2020 Collabora, Ltd.  + */ + +#include <linux/clk.h> 
>> > +#include <linux/component.h> +#include <linux/mfd/syscon.h> 
>> > +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include 
>> > <linux/module.h> +#include <linux/of_device.h> +#include 
>> > <linux/regmap.h> +#include <linux/videodev2.h> +#include 
>> > <drm/bridge/dw_mipi_dsi.h> +#include <drm/drm_crtc_helper.h> 
>> > +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_of.h> 
>> > +#include <drm/drm_print.h> + +#include "imx-drm.h" + 
>> > +#define DSI_PWR_UP                     0x04 +#define RESET 
>> > 0 +#define POWERUP                                BIT(0) + 
>> > +#define DSI_PHY_IF_CTRL                        0x5c +#define 
>> > PHY_IF_CTRL_RESET              0x0 + +#define 
>> > DSI_PHY_TST_CTRL0              0x64 +#define PHY_TESTCLK 
>> > BIT(1) +#define PHY_UNTESTCLK                  0 +#define 
>> > PHY_TESTCLR                    BIT(0) +#define PHY_UNTESTCLR 
>> > 0 + +#define DSI_PHY_TST_CTRL1              0x68 +#define 
>> > PHY_TESTEN                     BIT(16) +#define PHY_UNTESTEN 
>> > 0 +#define PHY_TESTDOUT(n)                        (((n) & 
>> > 0xff) << 8) +#define PHY_TESTDIN(n)                 (((n) & 
>> > 0xff) << 0) + +struct imx_mipi_dsi { +       struct 
>> > drm_encoder encoder; +       struct device *dev; + 
>> > struct regmap *mux_sel; +       struct dw_mipi_dsi *mipi_dsi; 
>> > +       struct clk *pllref_clk; + +       void __iomem *base; 
>> > +       unsigned int lane_mbps; +}; + +struct 
>> > dphy_pll_testdin_map { +       unsigned int max_mbps; + 
>> > u8 testdin; +}; + +/* The table is based on 27MHz DPHY pll 
>> > reference clock. */ +static const struct dphy_pll_testdin_map 
>> > dptdin_map[] = { +       {160, 0x04}, {180, 0x24}, {200, 
>> > 0x44}, {210, 0x06}, +       {240, 0x26}, {250, 0x46}, {270, 
>> > 0x08}, {300, 0x28}, +       {330, 0x48}, {360, 0x2a}, {400, 
>> > 0x4a}, {450, 0x0c}, +       {500, 0x2c}, {550, 0x0e}, {600, 
>> > 0x2e}, {650, 0x10}, +       {700, 0x30}, {750, 0x12}, {800, 
>> > 0x32}, {850, 0x14}, +       {900, 0x34}, {950, 0x54}, {1000, 
>> > 0x74} +}; + +static inline struct imx_mipi_dsi 
>> > *enc_to_dsi(struct drm_encoder *enc) +{ +       return 
>> > container_of(enc, struct imx_mipi_dsi, encoder); +} + +static 
>> > void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, 
>> > int ipu_di) +{ +       regmap_update_bits(dsi->mux_sel, 
>> > IOMUXC_GPR3, + 
>> > IMX6Q_GPR3_MIPI_MUX_CTL_MASK, + 
>> > ipu_di << IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT); +} + +static const 
>> > struct drm_encoder_funcs imx_mipi_dsi_encoder_funcs = { + 
>> > .destroy = imx_drm_encoder_destroy, +}; + +static bool 
>> > imx_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder, 
>> > +                                           const struct 
>> > drm_display_mode *mode, + 
>> > struct drm_display_mode *adj_mode) +{ +       return true; +} 
>> > + +static int imx_mipi_dsi_encoder_atomic_check(struct 
>> > drm_encoder *encoder, + 
>> > struct drm_crtc_state *crtc_state, + 
>> > struct drm_connector_state *conn) +{ +       struct 
>> > imx_crtc_state *imx_crtc_state = 
>> > to_imx_crtc_state(crtc_state); + +       /* The following 
>> > values are taken from dw_hdmi_imx_atomic_check */ + 
>> > imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24; + 
>> > imx_crtc_state->di_hsync_pin = 2; + 
>> > imx_crtc_state->di_vsync_pin = 3; + +       return 0; +} + 
>> > +static void imx_mipi_dsi_encoder_commit(struct drm_encoder 
>> > *encoder) +{ +       struct imx_mipi_dsi *dsi = 
>> > enc_to_dsi(encoder); +       int mux = 
>> > drm_of_encoder_active_port_id(dsi->dev->of_node, encoder); + 
>> > +       imx_mipi_dsi_set_ipu_di_mux(dsi, mux); +} + +static 
>> > void imx_mipi_dsi_encoder_disable(struct drm_encoder 
>> > *encoder) +{ +} + +static const struct 
>> > drm_encoder_helper_funcs imx_mipi_dsi_encoder_helpers = { 
>>  AFAIK (or at least this is the feedback I received) 
>> drm_encoder is kind of deprecated, and nowadays all is migrated 
>> to drm_bridge (encoders, bridges and panels). Of course, a 
>> drm_encoder is needed, as the DRM core expects one, but should 
>> just be a dummy object that you can probably create with just 
>> calling  drm_simple_encoder_init(). DRM maintainers, please 
>> shout if I am wrong. 
> 
> That certainly matches my position :-) I would also add that the 
> DRM encoder should be created in imx-drm-core.c or in 
> ipuv3-crtc.c, not here. 
>

Yes, I will do this change in v7 especially also because a new 
commit 62fbddda2f72 ("drm/imx: Use simple encoder") landed in 
-next  recently which broke the current imx6 implementation by 
removing the imx_drm_encoder_destroy() from imx-drm-core.c.

>> > +       .mode_fixup = imx_mipi_dsi_encoder_mode_fixup,
>> > +       .commit = imx_mipi_dsi_encoder_commit,
>> > +       .disable = imx_mipi_dsi_encoder_disable,
>> > +       .atomic_check = imx_mipi_dsi_encoder_atomic_check,
>> > +};
>> > +
>> > +static int imx_mipi_dsi_register(struct drm_device *drm,
>> > +                                struct imx_mipi_dsi *dsi)
>> > +{
>> > +       int ret;
>> > +
>> > +       ret = imx_drm_encoder_parse_of(drm, &dsi->encoder, dsi->dev->of_node);
>> > +       if (ret)
>> > +               return ret;
>> > +
>> > +       drm_encoder_helper_add(&dsi->encoder,
>> > +                              &imx_mipi_dsi_encoder_helpers);
>> > +       drm_encoder_init(drm, &dsi->encoder, &imx_mipi_dsi_encoder_funcs,
>> > +                        DRM_MODE_ENCODER_DSI, NULL);
>> > +       return 0;
>> > +}
>> > +
>> > +static enum drm_mode_status imx_mipi_dsi_mode_valid(void *priv_data,
>> > +                                       const struct drm_display_mode *mode)
>> > +{
>> > +       /*
>> > +        * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG
>> > +        * register is 11-bit.
>> > +        */
>> > +       if (mode->hdisplay > 0x7ff)
>> > +               return MODE_BAD_HVALUE;
>> > +
>> > +       /*
>> > +        * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG
>> > +        * register is 11-bit.
>> > +        */
>> > +       if (mode->vdisplay > 0x7ff)
>> > +               return MODE_BAD_VVALUE;
>> > +
>> > +       return MODE_OK;
>> > +}
>> > +
>> > +
>> > +static unsigned int max_mbps_to_testdin(unsigned int max_mbps)
>> > +{
>> > +       unsigned int i;
>> > +
>> > +       for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
>> > +               if (dptdin_map[i].max_mbps == max_mbps)
>> > +                       return dptdin_map[i].testdin;
>> > +
>> > +       return -EINVAL;
>> > +}
>> > +
>> > +static inline void dsi_write(struct imx_mipi_dsi *dsi, u32 reg, u32 val)
>> > +{
>> > +       writel(val, dsi->base + reg);
>> > +}
>> > +
>> > +static int imx_mipi_dsi_phy_init(void *priv_data)
>> > +{
>> > +       struct imx_mipi_dsi *dsi = priv_data;
>> > +       int testdin;
>> > +
>> > +       testdin = max_mbps_to_testdin(dsi->lane_mbps);
>> > +       if (testdin < 0) {
>> > +               DRM_DEV_ERROR(dsi->dev,
>> > +                             "failed to get testdin for %dmbps lane clock\n",
>> > +                             dsi->lane_mbps);
>> > +               return testdin;
>> > +       }
>> > +
>> > +       dsi_write(dsi, DSI_PHY_IF_CTRL, PHY_IF_CTRL_RESET);
>> > +       dsi_write(dsi, DSI_PWR_UP, POWERUP);
>> > +
>> > +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
>> > +       dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
>> > +                 PHY_TESTDIN(0x44));
>> > +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
>> > +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
>> > +       dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
>> > +                 PHY_TESTDIN(testdin));
>> > +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
>> > +       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
>> > +
>> > +       return 0;
>> > +}
>> > +
>> > +static int imx_mipi_dsi_get_lane_mbps(void *priv_data,
>> > +                                     const struct drm_display_mode *mode,
>> > +                                     unsigned long mode_flags, u32 lanes,
>> > +                                     u32 format, unsigned int *lane_mbps)
>> > +{
>> > +       struct imx_mipi_dsi *dsi = priv_data;
>> > +       int bpp;
>> > +       unsigned int i, target_mbps, mpclk;
>> > +       unsigned long pllref;
>> > +
>> > +       bpp = mipi_dsi_pixel_format_to_bpp(format);
>> > +       if (bpp < 0) {
>> > +               DRM_DEV_ERROR(dsi->dev, "failed to get bpp for format %d: %d\n",
>> > +                             format, bpp);
>> > +               return bpp;
>> > +       }
>> > +
>> > +       pllref = clk_get_rate(dsi->pllref_clk);
>> > +       if (pllref != 27000000)
>> > +               DRM_WARN("DSI pllref_clk not set to 27Mhz\n");
>> > +
>> > +       mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
>> > +       if (mpclk) {
>> > +               /* take 1/0.7 blanking overhead into consideration */
>> > +               target_mbps = (mpclk * (bpp / lanes) * 10) / 7;
>> > +       } else {
>> > +               DRM_DEV_ERROR(dsi->dev, "use default 1Gbps DPHY pll clock\n");
>> > +               target_mbps = 1000;
>> > +       }
>> > +
>> > +       DRM_DEV_DEBUG(dsi->dev, "target pllref_clk frequency is %uMbps\n",
>> > +                     target_mbps);
>> > +
>> > +       for (i = 0; i < ARRAY_SIZE(dptdin_map); i++) {
>> > +               if (target_mbps < dptdin_map[i].max_mbps) {
>> > +                       *lane_mbps = dptdin_map[i].max_mbps;
>> > +                       dsi->lane_mbps = *lane_mbps;
>> > +                       DRM_DEV_DEBUG(dsi->dev,
>> > +                                     "real pllref_clk frequency is %uMbps\n",
>> > +                                     *lane_mbps);
>> > +                       return 0;
>> > +               }
>> > +       }
>> > +
>> > +       DRM_DEV_ERROR(dsi->dev, "DPHY clock frequency %uMbps is out of range\n",
>> > +                     target_mbps);
>> > +
>> > +       return -EINVAL;
>> > +}
>> > +
>> > +static int
>> > +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
>> > +                          struct dw_mipi_dsi_dphy_timing *timing)
>> > +{
>> > +       timing->clk_hs2lp = 0x40;
>> > +       timing->clk_lp2hs = 0x40;
>> > +       timing->data_hs2lp = 0x40;
>> > +       timing->data_lp2hs = 0x40;
>> > +
>> > +       return 0;
>> > +}
>> > +
>> > +static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_imx6_phy_ops = {
>> > +       .init = imx_mipi_dsi_phy_init,
>> > +       .get_lane_mbps = imx_mipi_dsi_get_lane_mbps,
>> > +       .get_timing = dw_mipi_dsi_phy_get_timing,
>> > +};
>> > +
>> > +static struct dw_mipi_dsi_plat_data imx6q_mipi_dsi_drv_data = {
>> > +       .max_data_lanes = 2,
>> > +       .mode_valid = imx_mipi_dsi_mode_valid,
>> > +       .phy_ops = &dw_mipi_dsi_imx6_phy_ops,
>> > +};
>> > +
>> > +static const struct of_device_id imx_dsi_dt_ids[] = {
>> > +       {
>> > +               .compatible = "fsl,imx6q-mipi-dsi",
>> > +               .data = &imx6q_mipi_dsi_drv_data,
>> > +       },
>> > +       { /* sentinel */ }
>> > +};
>> > +MODULE_DEVICE_TABLE(of, imx_dsi_dt_ids);
>> > +
>> > +static int imx_mipi_dsi_bind(struct device *dev, struct device *master,
>> > +                            void *data)
>> > +{
>> > +       struct imx_mipi_dsi *dsi = dev_get_drvdata(dev);
>> > +       struct drm_device *drm = data;
>> > +       int ret;
>> > +
>> > +       ret = clk_prepare_enable(dsi->pllref_clk);
>> > +       if (ret) {
>> > +               DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
>> > +               return ret;
>> > +       }
>> > +
>> > +       ret = imx_mipi_dsi_register(drm, dsi);
>> > +       if (ret) {
>> > +               DRM_DEV_ERROR(dev, "Failed to register: %d\n", ret);
>> > +               return ret;
>> > +       }
>> > +
>> > +       ret = dw_mipi_dsi_bind(dsi->mipi_dsi, &dsi->encoder);
>> > +       if (ret) {
>> > +               DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
>> > +               return ret;
>> > +       }
>> > +
>> > +       return 0;
>> > +}
>> > +
>> > +static void imx_mipi_dsi_unbind(struct device *dev, struct device *master,
>> > +                               void *data)
>> > +{
>> > +       struct imx_mipi_dsi *dsi = dev_get_drvdata(dev);
>> > +
>> > +       dw_mipi_dsi_unbind(dsi->mipi_dsi);
>> > +
>> > +       clk_disable_unprepare(dsi->pllref_clk);
>> > +}
>> > +
>> > +static const struct component_ops imx_mipi_dsi_ops = {
>> > +       .bind   = imx_mipi_dsi_bind,
>> > +       .unbind = imx_mipi_dsi_unbind,
>> > +};
>> > +
>> > +static int imx_mipi_dsi_probe(struct platform_device *pdev)
>> > +{
>> > +       struct device *dev = &pdev->dev;
>> > +       const struct of_device_id *of_id = of_match_device(imx_dsi_dt_ids, dev);
>> > +       struct dw_mipi_dsi_plat_data *pdata = (struct dw_mipi_dsi_plat_data *) of_id->data;
>> > +       struct imx_mipi_dsi *dsi;
>> > +       struct resource *res;
>> > +       int ret;
>> > +
>> > +       dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
>> > +       if (!dsi)
>> > +               return -ENOMEM;
>> > +
>> > +       dsi->dev = dev;
>> > +
>> > +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> > +       dsi->base = devm_ioremap_resource(dev, res);
>> > +       if (IS_ERR(dsi->base)) {
>> > +               ret = PTR_ERR(dsi->base);
>> > +               DRM_DEV_ERROR(dev, "Unable to get dsi registers: %d\n", ret);
>> > +               return ret;
>> > +       }
>> > +
>> > +       dsi->pllref_clk = devm_clk_get(dev, "ref");
>> > +       if (IS_ERR(dsi->pllref_clk)) {
>> > +               ret = PTR_ERR(dsi->pllref_clk);
>> > +               DRM_DEV_ERROR(dev, "Unable to get pllref_clk: %d\n", ret);
>> > +               return ret;
>> > +       }
>> > +
>> > +       dsi->mux_sel = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr");
>> > +       if (IS_ERR(dsi->mux_sel)) {
>> > +               ret = PTR_ERR(dsi->mux_sel);
>> > +               DRM_DEV_ERROR(dev, "Failed to get GPR regmap: %d\n", ret);
>> > +               return ret;
>> > +       }
>> > +
>> > +       dev_set_drvdata(dev, dsi);
>> > +
>> > +       imx6q_mipi_dsi_drv_data.base = dsi->base;
>> > +       imx6q_mipi_dsi_drv_data.priv_data = dsi;
>> > +
>> > +       dsi->mipi_dsi = dw_mipi_dsi_probe(pdev, pdata);
>> > +       if (IS_ERR(dsi->mipi_dsi)) {
>> > +               ret = PTR_ERR(dsi->mipi_dsi);
>> > +               DRM_DEV_ERROR(dev, "Failed to probe DW DSI host: %d\n", ret);
>> > +               goto err_clkdisable;
>> > +       }
>> > +
>> > +       return component_add(&pdev->dev, &imx_mipi_dsi_ops);
>> > +
>> > +err_clkdisable:
>> > +       clk_disable_unprepare(dsi->pllref_clk);
>> > +       return ret;
>> > +}
>> > +
>> > +static int imx_mipi_dsi_remove(struct platform_device *pdev)
>> > +{
>> > +       component_del(&pdev->dev, &imx_mipi_dsi_ops);
>> > +       return 0;
>> > +}
>> > +
>> > +static struct platform_driver imx_mipi_dsi_driver = {
>> > +       .probe          = imx_mipi_dsi_probe,
>> > +       .remove         = imx_mipi_dsi_remove,
>> > +       .driver         = {
>> > +               .of_match_table = imx_dsi_dt_ids,
>> > +               .name   = "dw-mipi-dsi-imx6",
>> > +       },
>> > +};
>> > +module_platform_driver(imx_mipi_dsi_driver);
>> > +
>> > +MODULE_DESCRIPTION("i.MX6 MIPI DSI host controller driver");
>> > +MODULE_AUTHOR("Liu Ying <victor.liu-3arQi8VN3Tc@public.gmane.org>");
>> > +MODULE_AUTHOR("Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>");
>> > +MODULE_LICENSE("GPL");
>
> -- 
> Regards,
>
> Laurent Pinchart

[PATCH v6 5/8] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

[Adrian Ratiu]

This provides an example DT binding for the MIPI DSI host controller
present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.

Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Cc: Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Signed-off-by: Sjoerd Simons <sjoerd.simons-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Signed-off-by: Martyn Welch <martyn.welch-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Signed-off-by: Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
Changes since v5:
  - Fixed missing reg warning (Fabio)
  - Updated dt-schema and fixed warnings (Rob)

Changes since v4:
  - Fixed yaml binding to pass `make dt_binding_check dtbs_check`
  and addressed received binding feedback (Rob)

Changes since v3:
  - Added commit message (Neil)
  - Converted to yaml format (Neil)
  - Minor dt node + driver fixes (Rob)
  - Added small panel example to the host controller binding

Changes since v2:
  - Fixed commit tags (Emil)
---
 .../display/imx/fsl,mipi-dsi-imx6.yaml        | 139 ++++++++++++++++++
 1 file changed, 139 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
new file mode 100644
index 000000000000..10e289ea219a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
@@ -0,0 +1,139 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 DW MIPI DSI Host Controller
+
+maintainers:
+  - Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
+
+description: |
+  The i.MX6 DSI host controller is a Synopsys DesignWare MIPI DSI v1.01
+  IP block with a companion PHY IP.
+
+  These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
+  Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
+  the following device-specific properties.
+
+properties:
+  compatible:
+    items:
+      - const: fsl,imx6q-mipi-dsi
+      - const: snps,dw-mipi-dsi
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Module Clock
+      - description: DSI bus clock
+
+  clock-names:
+    items:
+      - const: ref
+      - const: pclk
+
+  fsl,gpr:
+    description: Phandle to the iomuxc-gpr region containing the multiplexer control register.
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+  ports:
+    type: object
+    description: |
+      A node containing DSI input & output port nodes with endpoint
+      definitions as documented in
+      Documentation/devicetree/bindings/media/video-interfaces.txt
+      Documentation/devicetree/bindings/graph.txt
+    properties:
+      port@0:
+        type: object
+        description:
+          DSI input port node, connected to the ltdc rgb output port.
+
+      port@1:
+        type: object
+        description:
+          DSI output port node, connected to a panel or a bridge input port"
+
+patternProperties:
+  "^panel@[0-3]$":
+    type: object
+    description: |
+      A node containing the panel or bridge description as documented in
+      Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+    properties:
+      port:
+        type: object
+        description:
+          Panel or bridge port node, connected to the DSI output port (port@1)
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |+
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/imx6qdl-clock.h>
+    #include <dt-bindings/gpio/gpio.h>
+
+    dsi: dsi@21e0000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+        reg = <0x021e0000 0x4000>;
+        interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+        fsl,gpr = <&gpr>;
+        clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+                 <&clks IMX6QDL_CLK_MIPI_IPG>;
+        clock-names = "ref", "pclk";
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            port@1 {
+                reg = <1>;
+                dsi_out: endpoint {
+                    remote-endpoint = <&panel_in>;
+                };
+            };
+        };
+
+        panel@0 {
+            compatible = "sharp,ls032b3sx01";
+            reg = <0>;
+            reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@0 {
+                    reg = <0>;
+                    panel_in: endpoint {
+                        remote-endpoint = <&dsi_out>;
+                    };
+                };
+            };
+        };
+    };
+
+...
-- 
2.26.0

Re: [PATCH v6 5/8] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

[Laurent Pinchart]

Hi Adrian,

Thank you for the patch.

On Tue, Apr 14, 2020 at 06:19:52PM +0300, Adrian Ratiu wrote:
> This provides an example DT binding for the MIPI DSI host controller
> present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.
> 
> Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> Cc: Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Tested-by: Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Signed-off-by: Sjoerd Simons <sjoerd.simons-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Signed-off-by: Martyn Welch <martyn.welch-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Signed-off-by: Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> ---
> Changes since v5:
>   - Fixed missing reg warning (Fabio)
>   - Updated dt-schema and fixed warnings (Rob)
> 
> Changes since v4:
>   - Fixed yaml binding to pass `make dt_binding_check dtbs_check`
>   and addressed received binding feedback (Rob)
> 
> Changes since v3:
>   - Added commit message (Neil)
>   - Converted to yaml format (Neil)
>   - Minor dt node + driver fixes (Rob)
>   - Added small panel example to the host controller binding
> 
> Changes since v2:
>   - Fixed commit tags (Emil)
> ---
>  .../display/imx/fsl,mipi-dsi-imx6.yaml        | 139 ++++++++++++++++++
>  1 file changed, 139 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
> new file mode 100644
> index 000000000000..10e289ea219a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
> @@ -0,0 +1,139 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX6 DW MIPI DSI Host Controller
> +
> +maintainers:
> +  - Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> +
> +description: |
> +  The i.MX6 DSI host controller is a Synopsys DesignWare MIPI DSI v1.01
> +  IP block with a companion PHY IP.
> +
> +  These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
> +  Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
> +  the following device-specific properties.

Not necessarily a prerequisite for this patch, but it would be nice to
get that converted to yaml, and included here with

allOf:
  $ref: ../bridge/snps,dw-mipi-dsi.yaml#

(assuming that's how the file will be called).

> +
> +properties:
> +  compatible:
> +    items:
> +      - const: fsl,imx6q-mipi-dsi
> +      - const: snps,dw-mipi-dsi
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Module Clock
> +      - description: DSI bus clock
> +
> +  clock-names:
> +    items:
> +      - const: ref
> +      - const: pclk
> +
> +  fsl,gpr:
> +    description: Phandle to the iomuxc-gpr region containing the multiplexer control register.

Could you please wrap liens at a 80 columns boundary ?

> +    $ref: /schemas/types.yaml#/definitions/phandle
> +
> +  ports:
> +    type: object
> +    description: |
> +      A node containing DSI input & output port nodes with endpoint
> +      definitions as documented in
> +      Documentation/devicetree/bindings/media/video-interfaces.txt
> +      Documentation/devicetree/bindings/graph.txt
> +    properties:

You should add

       '#address-cells':
         const: 1

       '#size-cells':
         const: 0

> +      port@0:
> +        type: object
> +        description:
> +          DSI input port node, connected to the ltdc rgb output port.
> +
> +      port@1:
> +        type: object
> +        description:
> +          DSI output port node, connected to a panel or a bridge input port"


Should this be "RGB output port node" ? And s/"/./

And here you should add

       additionalProperties: false

> +
> +patternProperties:
> +  "^panel@[0-3]$":
> +    type: object
> +    description: |
> +      A node containing the panel or bridge description as documented in
> +      Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
> +    properties:
> +      port:
> +        type: object
> +        description:
> +          Panel or bridge port node, connected to the DSI output port (port@1)

Does this belong here ? I think the port property for the panel needs to
be described in the panel's binding instead.

> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 0

These two properties are not pattern properties, right ? Should they be
listed under the properties above ?

> +
> +required:
> +  - "#address-cells"
> +  - "#size-cells"
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |+
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/imx6qdl-clock.h>
> +    #include <dt-bindings/gpio/gpio.h>

Alphabetical order ?

> +
> +    dsi: dsi@21e0000 {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +        compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
> +        reg = <0x021e0000 0x4000>;
> +        interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
> +        fsl,gpr = <&gpr>;
> +        clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
> +                 <&clks IMX6QDL_CLK_MIPI_IPG>;
> +        clock-names = "ref", "pclk";
> +
> +        ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +            port@1 {
> +                reg = <1>;
> +                dsi_out: endpoint {
> +                    remote-endpoint = <&panel_in>;
> +                };
> +            };
> +        };
> +
> +        panel@0 {
> +            compatible = "sharp,ls032b3sx01";
> +            reg = <0>;
> +            reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;
> +            ports {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +                port@0 {
> +                    reg = <0>;
> +                    panel_in: endpoint {
> +                        remote-endpoint = <&dsi_out>;
> +                    };
> +                };
> +            };
> +        };
> +    };
> +
> +...

-- 
Regards,

Laurent Pinchart

Re: [PATCH v6 5/8] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

[Adrian Ratiu]

On Tue, 14 Apr 2020, Laurent Pinchart 
<laurent.pinchart@ideasonboard.com> wrote:
> Hi Adrian, 
> 
> Thank you for the patch. 

Hi Laurent,

Thank you for the review - you raised some good points which will 
be addressed in the next revision (will leave this on review a bit 
more).

I will also convert the dw_mipi_dsi.txt to yaml as you suggest and 
send that as a separate patch.

Best wishes,
Adrian

> 
> On Tue, Apr 14, 2020 at 06:19:52PM +0300, Adrian Ratiu wrote: 
>> This provides an example DT binding for the MIPI DSI host 
>> controller present on the i.MX6 SoC based on Synopsis 
>> DesignWare v1.01 IP.   Cc: Rob Herring <robh@kernel.org> Cc: 
>> Neil Armstrong <narmstrong@baylibre.com> Cc: Fabio Estevam 
>> <festevam@gmail.com> Cc: devicetree@vger.kernel.org Tested-by: 
>> Adrian Pop <pop.adrian61@gmail.com> Tested-by: Arnaud Ferraris 
>> <arnaud.ferraris@collabora.com> Signed-off-by: Sjoerd Simons 
>> <sjoerd.simons@collabora.com> Signed-off-by: Martyn Welch 
>> <martyn.welch@collabora.com> Signed-off-by: Adrian Ratiu 
>> <adrian.ratiu@collabora.com> --- Changes since v5: 
>>   - Fixed missing reg warning (Fabio) - Updated dt-schema and 
>>   fixed warnings (Rob) 
>>  Changes since v4: 
>>   - Fixed yaml binding to pass `make dt_binding_check 
>>   dtbs_check` and addressed received binding feedback (Rob) 
>>  Changes since v3: 
>>   - Added commit message (Neil) - Converted to yaml format 
>>   (Neil) - Minor dt node + driver fixes (Rob) - Added small 
>>   panel example to the host controller binding 
>>  Changes since v2: 
>>   - Fixed commit tags (Emil) 
>> --- 
>>  .../display/imx/fsl,mipi-dsi-imx6.yaml        | 139 
>>  ++++++++++++++++++ 1 file changed, 139 insertions(+) create 
>>  mode 100644 
>>  Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
>>  diff --git 
>> a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
>> b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
>> new file mode 100644 index 000000000000..10e289ea219a --- 
>> /dev/null +++ 
>> b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
>> @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR 
>> BSD-2-Clause) +%YAML 1.2 +--- +$id: 
>> http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml# 
>> +$schema: http://devicetree.org/meta-schemas/core.yaml# + 
>> +title: Freescale i.MX6 DW MIPI DSI Host Controller + 
>> +maintainers: +  - Adrian Ratiu <adrian.ratiu@collabora.com> + 
>> +description: | +  The i.MX6 DSI host controller is a Synopsys 
>> DesignWare MIPI DSI v1.01 +  IP block with a companion PHY IP. 
>> + +  These DT bindings follow the Synopsys DW MIPI DSI bindings 
>> defined in + 
>> Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
>> with +  the following device-specific properties. 
> 
> Not necessarily a prerequisite for this patch, but it would be 
> nice to get that converted to yaml, and included here with 
> 
> allOf: 
>   $ref: ../bridge/snps,dw-mipi-dsi.yaml# 
> 
> (assuming that's how the file will be called). 
>

Yes, I will do this conversion but in a separate patch to avoid 
making this series bigger.

Thanks,
Adrian

>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - const: fsl,imx6q-mipi-dsi
>> +      - const: snps,dw-mipi-dsi
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +  clocks:
>> +    items:
>> +      - description: Module Clock
>> +      - description: DSI bus clock
>> +
>> +  clock-names:
>> +    items:
>> +      - const: ref
>> +      - const: pclk
>> +
>> +  fsl,gpr:
>> +    description: Phandle to the iomuxc-gpr region containing the multiplexer control register.
>
> Could you please wrap liens at a 80 columns boundary ?
>
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +
>> +  ports:
>> +    type: object
>> +    description: |
>> +      A node containing DSI input & output port nodes with endpoint
>> +      definitions as documented in
>> +      Documentation/devicetree/bindings/media/video-interfaces.txt
>> +      Documentation/devicetree/bindings/graph.txt
>> +    properties:
>
> You should add
>
>        '#address-cells':
>          const: 1
>
>        '#size-cells':
>          const: 0
>
>> +      port@0:
>> +        type: object
>> +        description:
>> +          DSI input port node, connected to the ltdc rgb output port.
>> +
>> +      port@1:
>> +        type: object
>> +        description:
>> +          DSI output port node, connected to a panel or a bridge input port"
>
>
> Should this be "RGB output port node" ? And s/"/./
>
> And here you should add
>
>        additionalProperties: false
>
>> +
>> +patternProperties:
>> +  "^panel@[0-3]$":
>> +    type: object
>> +    description: |
>> +      A node containing the panel or bridge description as documented in
>> +      Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
>> +    properties:
>> +      port:
>> +        type: object
>> +        description:
>> +          Panel or bridge port node, connected to the DSI output port (port@1)
>
> Does this belong here ? I think the port property for the panel needs to
> be described in the panel's binding instead.
>
>> +
>> +  "#address-cells":
>> +    const: 1
>> +
>> +  "#size-cells":
>> +    const: 0
>
> These two properties are not pattern properties, right ? Should they be
> listed under the properties above ?
>
>> +
>> +required:
>> +  - "#address-cells"
>> +  - "#size-cells"
>> +  - compatible
>> +  - reg
>> +  - interrupts
>> +  - clocks
>> +  - clock-names
>> +  - ports
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |+
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/clock/imx6qdl-clock.h>
>> +    #include <dt-bindings/gpio/gpio.h>
>
> Alphabetical order ?
>
>> +
>> +    dsi: dsi@21e0000 {
>> +        #address-cells = <1>;
>> +        #size-cells = <0>;
>> +        compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
>> +        reg = <0x021e0000 0x4000>;
>> +        interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
>> +        fsl,gpr = <&gpr>;
>> +        clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
>> +                 <&clks IMX6QDL_CLK_MIPI_IPG>;
>> +        clock-names = "ref", "pclk";
>> +
>> +        ports {
>> +            #address-cells = <1>;
>> +            #size-cells = <0>;
>> +            port@1 {
>> +                reg = <1>;
>> +                dsi_out: endpoint {
>> +                    remote-endpoint = <&panel_in>;
>> +                };
>> +            };
>> +        };
>> +
>> +        panel@0 {
>> +            compatible = "sharp,ls032b3sx01";
>> +            reg = <0>;
>> +            reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;
>> +            ports {
>> +                #address-cells = <1>;
>> +                #size-cells = <0>;
>> +                port@0 {
>> +                    reg = <0>;
>> +                    panel_in: endpoint {
>> +                        remote-endpoint = <&dsi_out>;
>> +                    };
>> +                };
>> +            };
>> +        };
>> +    };
>> +
>> +...
>
> -- 
> Regards,
>
> Laurent Pinchart

[PATCH v6 6/8] drm: stm: dw-mipi-dsi: let the bridge handle the HW version check

[Adrian Ratiu]

The stm mipi-dsi platform driver added a version test in
commit fa6251a747b7 ("drm/stm: dsi: check hardware version")
so that HW revisions other than v1.3x get rejected. The rockchip
driver had no such check and just assumed register layouts are
v1.3x compatible.

Having such tests was a good idea because only v130/v131 layouts
were supported at the time, however since adding multiple layout
support in the bridge, the version is automatically checked for
all drivers, compatible layouts get picked and unsupported HW is
automatically rejected by the bridge, so there's no use keeping
the test in the stm driver.

The main reason prompting this change is that the stm driver
test immediately disabled the peripheral clock after reading
the version, making the bridge read version 0x0 immediately
after in its own probe(), so we move the clock disabling after
the bridge does the version test.

Tested on STM32F769 and STM32MP1.

Cc: linux-stm32-XDFAJ8BFU24N7RejjzZ/Li2xQDfSxrLKVpNB7YpNyf8@public.gmane.org
Reported-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Signed-off-by: Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
New in v6.
---
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 2e1f2664495d..7218e405d7e2 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -402,15 +402,6 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
 		goto err_dsi_probe;
 	}
 
-	dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
-	clk_disable_unprepare(pclk);
-
-	if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
-		ret = -ENODEV;
-		DRM_ERROR("bad dsi hardware version\n");
-		goto err_dsi_probe;
-	}
-
 	dw_mipi_dsi_stm_plat_data.base = dsi->base;
 	dw_mipi_dsi_stm_plat_data.priv_data = dsi;
 
@@ -423,6 +414,9 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
 		goto err_dsi_probe;
 	}
 
+	dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
+	clk_disable_unprepare(pclk);
+
 	return 0;
 
 err_dsi_probe:
-- 
2.26.0

[PATCH v6 7/8] drm: bridge: dw-mipi-dsi: split low power cfg register into fields

[Adrian Ratiu]

According to the Host Registers documentation for IMX, STM and RK
the LP cfg register should not be written entirely in one go because
some bits are reserved and should be kept to reset values, for eg.
BIT(15) which is reserved in all versions.

This also cleans up the code by removing the the ugly defines
and making field ranges & values written more explicit.

Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Signed-off-by: Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
New in v6.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 105 ++++++------------
 1 file changed, 33 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 0ce2697d17a3..cbbe31c0dbac 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -120,60 +120,6 @@
 #define DSI_TO_CNT_CFG_V101		0x40
 #define DSI_PCKHDL_CFG_V101		0x18
 
-#define MAX_RD_PKT_SIZE_LP		BIT(24)
-#define DCS_LW_TX_LP			BIT(19)
-#define DCS_SR_0P_TX_LP			BIT(18)
-#define DCS_SW_1P_TX_LP			BIT(17)
-#define DCS_SW_0P_TX_LP			BIT(16)
-#define GEN_LW_TX_LP			BIT(14)
-#define GEN_SR_2P_TX_LP			BIT(13)
-#define GEN_SR_1P_TX_LP			BIT(12)
-#define GEN_SR_0P_TX_LP			BIT(11)
-#define GEN_SW_2P_TX_LP			BIT(10)
-#define GEN_SW_1P_TX_LP			BIT(9)
-#define GEN_SW_0P_TX_LP			BIT(8)
-#define TEAR_FX_EN			BIT(0)
-
-#define CMD_MODE_ALL_LP			(MAX_RD_PKT_SIZE_LP | \
-					 DCS_LW_TX_LP | \
-					 DCS_SR_0P_TX_LP | \
-					 DCS_SW_1P_TX_LP | \
-					 DCS_SW_0P_TX_LP | \
-					 GEN_LW_TX_LP | \
-					 GEN_SR_2P_TX_LP | \
-					 GEN_SR_1P_TX_LP | \
-					 GEN_SR_0P_TX_LP | \
-					 GEN_SW_2P_TX_LP | \
-					 GEN_SW_1P_TX_LP | \
-					 GEN_SW_0P_TX_LP)
-
-#define EN_TEAR_FX_V101			BIT(14)
-#define DCS_LW_TX_LP_V101		BIT(12)
-#define GEN_LW_TX_LP_V101		BIT(11)
-#define MAX_RD_PKT_SIZE_LP_V101		BIT(10)
-#define DCS_SW_2P_TX_LP_V101		BIT(9)
-#define DCS_SW_1P_TX_LP_V101		BIT(8)
-#define DCS_SW_0P_TX_LP_V101		BIT(7)
-#define GEN_SR_2P_TX_LP_V101		BIT(6)
-#define GEN_SR_1P_TX_LP_V101		BIT(5)
-#define GEN_SR_0P_TX_LP_V101		BIT(4)
-#define GEN_SW_2P_TX_LP_V101		BIT(3)
-#define GEN_SW_1P_TX_LP_V101		BIT(2)
-#define GEN_SW_0P_TX_LP_V101		BIT(1)
-
-#define CMD_MODE_ALL_LP_V101		(DCS_LW_TX_LP_V101 | \
-					 GEN_LW_TX_LP_V101 | \
-					 MAX_RD_PKT_SIZE_LP_V101 | \
-					 DCS_SW_2P_TX_LP_V101 | \
-					 DCS_SW_1P_TX_LP_V101 | \
-					 DCS_SW_0P_TX_LP_V101 | \
-					 GEN_SR_2P_TX_LP_V101 | \
-					 GEN_SR_1P_TX_LP_V101 | \
-					 GEN_SR_0P_TX_LP_V101 | \
-					 GEN_SW_2P_TX_LP_V101 | \
-					 GEN_SW_1P_TX_LP_V101 | \
-					 GEN_SW_0P_TX_LP_V101)
-
 #define DSI_GEN_HDR			0x6c
 #define DSI_GEN_PLD_DATA		0x70
 
@@ -257,7 +203,11 @@ struct dw_mipi_dsi {
 	struct regmap_field	*field_dpi_vsync_active_low;
 	struct regmap_field	*field_dpi_hsync_active_low;
 	struct regmap_field	*field_cmd_mode_ack_rqst_en;
-	struct regmap_field	*field_cmd_mode_all_lp_en;
+	struct regmap_field	*field_cmd_mode_gen_sw_sr_en;
+	struct regmap_field	*field_cmd_mode_dcs_sw_sr_en;
+	struct regmap_field	*field_cmd_mode_gen_lw_en;
+	struct regmap_field	*field_cmd_mode_dcs_lw_en;
+	struct regmap_field	*field_cmd_mode_max_rd_pkt_size;
 	struct regmap_field	*field_cmd_mode_en;
 	struct regmap_field	*field_cmd_pkt_status;
 	struct regmap_field	*field_vid_mode_en;
@@ -315,7 +265,11 @@ struct dw_mipi_dsi_variant {
 	struct reg_field	cfg_dpi_hsync_active_low;
 	struct reg_field	cfg_cmd_mode_en;
 	struct reg_field	cfg_cmd_mode_ack_rqst_en;
-	struct reg_field	cfg_cmd_mode_all_lp_en;
+	struct reg_field	cfg_cmd_mode_gen_sw_sr_en;
+	struct reg_field	cfg_cmd_mode_dcs_sw_sr_en;
+	struct reg_field	cfg_cmd_mode_gen_lw_en;
+	struct reg_field	cfg_cmd_mode_dcs_lw_en;
+	struct reg_field	cfg_cmd_mode_max_rd_pkt_size;
 	struct reg_field	cfg_cmd_pkt_status;
 	struct reg_field	cfg_vid_mode_en;
 	struct reg_field	cfg_vid_mode_type;
@@ -366,7 +320,11 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
 	.cfg_dpi_vsync_active_low =	REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
 	.cfg_dpi_hsync_active_low =	REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
 	.cfg_cmd_mode_ack_rqst_en =	REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
-	.cfg_cmd_mode_all_lp_en =	REG_FIELD(DSI_CMD_MODE_CFG, 8, 24),
+	.cfg_cmd_mode_gen_sw_sr_en =	REG_FIELD(DSI_CMD_MODE_CFG, 8, 13),
+	.cfg_cmd_mode_gen_lw_en =	REG_FIELD(DSI_CMD_MODE_CFG, 14, 14),
+	.cfg_cmd_mode_dcs_sw_sr_en =	REG_FIELD(DSI_CMD_MODE_CFG, 16, 18),
+	.cfg_cmd_mode_dcs_lw_en =	REG_FIELD(DSI_CMD_MODE_CFG, 19, 19),
+	.cfg_cmd_mode_max_rd_pkt_size =	REG_FIELD(DSI_CMD_MODE_CFG, 24, 24),
 	.cfg_cmd_mode_en =		REG_FIELD(DSI_MODE_CFG, 0, 31),
 	.cfg_cmd_pkt_status =		REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
 	.cfg_vid_mode_en =		REG_FIELD(DSI_MODE_CFG, 0, 31),
@@ -418,7 +376,11 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
 	.cfg_dpi_vsync_active_low =	REG_FIELD(DSI_DPI_CFG, 6, 6),
 	.cfg_dpi_hsync_active_low =	REG_FIELD(DSI_DPI_CFG, 7, 7),
 	.cfg_cmd_mode_en =		REG_FIELD(DSI_CMD_MODE_CFG_V101, 0, 0),
-	.cfg_cmd_mode_all_lp_en =	REG_FIELD(DSI_CMD_MODE_CFG_V101, 1, 12),
+	.cfg_cmd_mode_gen_sw_sr_en =	REG_FIELD(DSI_CMD_MODE_CFG, 1, 6),
+	.cfg_cmd_mode_dcs_sw_sr_en =	REG_FIELD(DSI_CMD_MODE_CFG, 7, 9),
+	.cfg_cmd_mode_max_rd_pkt_size =	REG_FIELD(DSI_CMD_MODE_CFG, 10, 10),
+	.cfg_cmd_mode_gen_lw_en =	REG_FIELD(DSI_CMD_MODE_CFG, 11, 11),
+	.cfg_cmd_mode_dcs_lw_en =	REG_FIELD(DSI_CMD_MODE_CFG, 12, 12),
 	.cfg_cmd_mode_ack_rqst_en =	REG_FIELD(DSI_CMD_MODE_CFG_V101, 13, 13),
 	.cfg_cmd_pkt_status =		REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 14),
 	.cfg_vid_mode_en =		REG_FIELD(DSI_VID_MODE_CFG_V101, 0, 0),
@@ -554,23 +516,18 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 				   const struct mipi_dsi_msg *msg)
 {
 	bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
-	u32 cmd_mode_lp = 0;
-
-	switch (dsi->hw_version) {
-	case HWVER_130:
-	case HWVER_131:
-		cmd_mode_lp = CMD_MODE_ALL_LP;
-		break;
-	case HWVER_101:
-		cmd_mode_lp = CMD_MODE_ALL_LP_V101;
-		break;
-	}
 
 	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
 		regmap_field_write(dsi->field_cmd_mode_ack_rqst_en, 1);
 
-	if (lpm)
-		regmap_field_write(dsi->field_cmd_mode_all_lp_en, cmd_mode_lp);
+	if (lpm) {
+		regmap_field_write(dsi->field_cmd_mode_gen_sw_sr_en,
+				   ENABLE_LOW_POWER);
+		regmap_field_write(dsi->field_cmd_mode_dcs_sw_sr_en, 7);
+		regmap_field_write(dsi->field_cmd_mode_gen_lw_en, 1);
+		regmap_field_write(dsi->field_cmd_mode_dcs_lw_en, 1);
+		regmap_field_write(dsi->field_cmd_mode_max_rd_pkt_size, 1);
+	}
 
 	regmap_field_write(dsi->field_phy_txrequestclkhs, lpm ? 0 : 1);
 }
@@ -1252,7 +1209,11 @@ static int dw_mipi_dsi_regmap_fields_init(struct dw_mipi_dsi *dsi)
 	INIT_FIELD(dpi_vsync_active_low);
 	INIT_FIELD(dpi_hsync_active_low);
 	INIT_FIELD(cmd_mode_ack_rqst_en);
-	INIT_FIELD(cmd_mode_all_lp_en);
+	INIT_FIELD(cmd_mode_gen_sw_sr_en);
+	INIT_FIELD(cmd_mode_dcs_sw_sr_en);
+	INIT_FIELD(cmd_mode_gen_lw_en);
+	INIT_FIELD(cmd_mode_dcs_lw_en);
+	INIT_FIELD(cmd_mode_max_rd_pkt_size);
 	INIT_FIELD(cmd_mode_en);
 	INIT_FIELD(cmd_pkt_status);
 	INIT_FIELD(vid_mode_en);
-- 
2.26.0

[PATCH v6 8/8] drm: bridge: dw-mipi-dsi: fix bad register field offsets

[Adrian Ratiu]

According to the DSI Host Registers sections available in the IMX,
STM and RK ref manuals for 1.01, 1.30 and 1.31, the register fields
are smaller or bigger than what's coded in the driver, leading to
r/w in reserved spaces which might cause undefined behaviours.

Tested-by: Adrian Pop <pop.adrian61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Arnaud Ferraris <arnaud.ferraris-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Signed-off-by: Adrian Ratiu <adrian.ratiu-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
New in v6.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 46 +++++++++----------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index cbbe31c0dbac..7f6e3d1e2ad2 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -316,7 +316,7 @@ struct dw_mipi_dsi_variant {
 static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
 	.cfg_dpi_color_coding =		REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
 	.cfg_dpi_18loosely_en =		REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
-	.cfg_dpi_vid =			REG_FIELD(DSI_DPI_VCID, 0, 2),
+	.cfg_dpi_vid =			REG_FIELD(DSI_DPI_VCID, 0, 1),
 	.cfg_dpi_vsync_active_low =	REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
 	.cfg_dpi_hsync_active_low =	REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
 	.cfg_cmd_mode_ack_rqst_en =	REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
@@ -325,29 +325,29 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
 	.cfg_cmd_mode_dcs_sw_sr_en =	REG_FIELD(DSI_CMD_MODE_CFG, 16, 18),
 	.cfg_cmd_mode_dcs_lw_en =	REG_FIELD(DSI_CMD_MODE_CFG, 19, 19),
 	.cfg_cmd_mode_max_rd_pkt_size =	REG_FIELD(DSI_CMD_MODE_CFG, 24, 24),
-	.cfg_cmd_mode_en =		REG_FIELD(DSI_MODE_CFG, 0, 31),
-	.cfg_cmd_pkt_status =		REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
-	.cfg_vid_mode_en =		REG_FIELD(DSI_MODE_CFG, 0, 31),
+	.cfg_cmd_mode_en =		REG_FIELD(DSI_MODE_CFG, 0, 0),
+	.cfg_cmd_pkt_status =		REG_FIELD(DSI_CMD_PKT_STATUS, 0, 6),
+	.cfg_vid_mode_en =		REG_FIELD(DSI_MODE_CFG, 0, 0),
 	.cfg_vid_mode_type =		REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
 	.cfg_vid_mode_low_power =	REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
 	.cfg_vid_mode_vpg_en =		REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
 	.cfg_vid_mode_vpg_horiz =	REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
-	.cfg_vid_pkt_size =		REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
-	.cfg_vid_hsa_time =		REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
-	.cfg_vid_hbp_time =		REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
-	.cfg_vid_hline_time =		REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
-	.cfg_vid_vsa_time =		REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
-	.cfg_vid_vbp_time =		REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
-	.cfg_vid_vfp_time =		REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
-	.cfg_vid_vactive_time =		REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
+	.cfg_vid_pkt_size =		REG_FIELD(DSI_VID_PKT_SIZE, 0, 13),
+	.cfg_vid_hsa_time =		REG_FIELD(DSI_VID_HSA_TIME, 0, 11),
+	.cfg_vid_hbp_time =		REG_FIELD(DSI_VID_HBP_TIME, 0, 11),
+	.cfg_vid_hline_time =		REG_FIELD(DSI_VID_HLINE_TIME, 0, 14),
+	.cfg_vid_vsa_time =		REG_FIELD(DSI_VID_VSA_LINES, 0, 9),
+	.cfg_vid_vbp_time =		REG_FIELD(DSI_VID_VBP_LINES, 0, 9),
+	.cfg_vid_vfp_time =		REG_FIELD(DSI_VID_VFP_LINES, 0, 9),
+	.cfg_vid_vactive_time =		REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 13),
 	.cfg_phy_txrequestclkhs =	REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
-	.cfg_phy_bta_time =		REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
-	.cfg_phy_max_rd_time =		REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
+	.cfg_phy_bta_time =		REG_FIELD(DSI_BTA_TO_CNT, 0, 15),
+	.cfg_phy_max_rd_time =		REG_FIELD(DSI_PHY_TMR_CFG, 0, 14),
 	.cfg_phy_lp2hs_time =		REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
 	.cfg_phy_hs2lp_time =		REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
-	.cfg_phy_max_rd_time_v131 =	REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
-	.cfg_phy_lp2hs_time_v131 =	REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
-	.cfg_phy_hs2lp_time_v131 =	REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
+	.cfg_phy_max_rd_time_v131 =	REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 14),
+	.cfg_phy_lp2hs_time_v131 =	REG_FIELD(DSI_PHY_TMR_CFG, 0, 9),
+	.cfg_phy_hs2lp_time_v131 =	REG_FIELD(DSI_PHY_TMR_CFG, 16, 25),
 	.cfg_phy_clklp2hs_time =	REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
 	.cfg_phy_clkhs2lp_time =	REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 31),
 	.cfg_phy_testclr =		REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0),
@@ -361,11 +361,11 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
 	.cfg_pckhdl_cfg =		REG_FIELD(DSI_PCKHDL_CFG, 0, 4),
 	.cfg_hstx_timeout_counter =	REG_FIELD(DSI_TO_CNT_CFG, 16, 31),
 	.cfg_lprx_timeout_counter =	REG_FIELD(DSI_TO_CNT_CFG, 0, 15),
-	.cfg_int_stat0 =		REG_FIELD(DSI_INT_ST0, 0, 31),
-	.cfg_int_stat1 =		REG_FIELD(DSI_INT_ST1, 0, 31),
-	.cfg_int_mask0 =		REG_FIELD(DSI_INT_MSK0, 0, 31),
-	.cfg_int_mask1 =		REG_FIELD(DSI_INT_MSK1, 0, 31),
-	.cfg_gen_hdr =			REG_FIELD(DSI_GEN_HDR, 0, 31),
+	.cfg_int_stat0 =		REG_FIELD(DSI_INT_ST0, 0, 20),
+	.cfg_int_stat1 =		REG_FIELD(DSI_INT_ST1, 0, 12),
+	.cfg_int_mask0 =		REG_FIELD(DSI_INT_MSK0, 0, 20),
+	.cfg_int_mask1 =		REG_FIELD(DSI_INT_MSK1, 0, 12),
+	.cfg_gen_hdr =			REG_FIELD(DSI_GEN_HDR, 0, 23),
 	.cfg_gen_payload =		REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
 };
 
@@ -382,7 +382,7 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
 	.cfg_cmd_mode_gen_lw_en =	REG_FIELD(DSI_CMD_MODE_CFG, 11, 11),
 	.cfg_cmd_mode_dcs_lw_en =	REG_FIELD(DSI_CMD_MODE_CFG, 12, 12),
 	.cfg_cmd_mode_ack_rqst_en =	REG_FIELD(DSI_CMD_MODE_CFG_V101, 13, 13),
-	.cfg_cmd_pkt_status =		REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 14),
+	.cfg_cmd_pkt_status =		REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 6),
 	.cfg_vid_mode_en =		REG_FIELD(DSI_VID_MODE_CFG_V101, 0, 0),
 	.cfg_vid_mode_type =		REG_FIELD(DSI_VID_MODE_CFG_V101, 1, 2),
 	.cfg_vid_mode_low_power =	REG_FIELD(DSI_VID_MODE_CFG_V101, 3, 8),
-- 
2.26.0