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Wed, 22 Oct 2025 19:52:23 +0800 (CST) Message-ID: <8b569a35-3913-4dfe-a586-7ec9669edbc1@cixtech.com> Date: Wed, 22 Oct 2025 19:52:23 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] PCI: dw-rockchip: Add L1sub support To: Shawn Lin , Heiko Stuebner , Manivannan Sadhasivam , Bjorn Helgaas Cc: linux-rockchip@lists.infradead.org, Niklas Cassel , linux-pci@vger.kernel.org References: <1761132954-177344-1-git-send-email-shawn.lin@rock-chips.com> Content-Language: en-US From: Hans Zhang In-Reply-To: <1761132954-177344-1-git-send-email-shawn.lin@rock-chips.com> X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CB:EE_|PS1PPFEF7C8A25D:EE_ X-MS-Office365-Filtering-Correlation-Id: e99fed55-709a-44f0-440f-08de1161776f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?B?MGYrRy9CazV1NlE2MXRma0QxcXF0MHVYUCsrZFBlcVE0Wkc1ZDFhS1dKUGNP?= =?utf-8?B?UnovYUdkTmdjSFRnL1MxY2V2YlBCZjNqTCsvVHJjM25QSFFEcFQ5RTR2dzVr?= =?utf-8?B?eDFPMDRwTGNwVm9NOTVNcmdmamVBblF2WVZKaUV4cmVIM3dWMm9KUDZMSVFT?= =?utf-8?B?VUZneFlHM0haZGZib2pUaDhOMVhSM2hrb3Jic0hrUFY0Q3NzUGE4b1ZpUmtu?= =?utf-8?B?NDU5L0dEVTJ0NlNTUFN2akVuc0hmNTlyR0dkdDNST2tMZHh2akpDYWVVbEIr?= =?utf-8?B?MnB5elhBTGgxTFRIbkc4ZUxibnA5bmo1RTlKUHh3am9ET25VcUtMQ1ArcnBL?= =?utf-8?B?MXU2S3NyL3RkUHE0ZFlXZUVXbHRSc0Z3S2pSQWlWeWZTckZxdEJVelZ0NWxZ?= =?utf-8?B?eENCS1JVYjZ3djNadE45WjlOa25TTUlQN1VSblhnbDlwZVZLRll0TmM3Z2xo?= =?utf-8?B?aFVPN3JxRDJVUFdaSTdOSzdCNmZHdi9KVjR4MU1WdjVvazdjZXNDU0w2YVBC?= =?utf-8?B?ZmMzbjhjZk1kOUFiTXFYV0pibkorTTNNWEZtbm84SzFvNDRuUU5HU0dGaTJy?= =?utf-8?B?T1poOTRUTE1md3ZwYnoxYkxnZit2TjAwZU96TUpmNEJJbWJ2Z3JFZ2FORGZw?= =?utf-8?B?KzE1WjNSV0JjcThUcWxaaGlnZE9yTTB3TUFTd3lHWXdTYmM0aWw5WVhHMTdC?= =?utf-8?B?MVl5NVVnM3JWdUEwTGdTQVhvMXp2a1FmNFVHMTU1N0I3WVlSNEYwL2xiNHRJ?= =?utf-8?B?UmN6dFhSbkJqWmZKRUtwWXFBTnVDY1pLNUJnUDAweFhBQ0I0RDF1cHlSeE5m?= =?utf-8?B?Z2NiNk9nUGFTVE13S1R6aW1wcktHcVZEMCsxdlY5Zi85ZHQ1a3FEU3dDMC9v?= =?utf-8?B?MUpIUkRTY1NGSzNUVXJaU0JIcFdYUzgrM3NQUWJqL0xoUlBYQWxEbE1OTTFj?= =?utf-8?B?WmpYRWhXclF1Um1MbE5JaG5YdkpVdUp5cDdSSkFxd0lhTExhU3RRNWhDT2cv?= =?utf-8?B?ZGRpSTRtOVBCeWpNYUlyR29wZVRlRWU4UEc5b0ptdFlkdWhTWXh2WmJCS0NB?= =?utf-8?B?cy9WVmZSaGw3aTR5cXlmRWdHVTZ5MVF5YXFhVjIyRzBQMHE1clhkbmVjeWd4?= =?utf-8?B?WTc0TlFiVWV6a09QclJSZlloWVhmQUd5NmsyQjdvNkNlQy9MYlFZVzdjb1Nn?= =?utf-8?B?RERUZ2RQSHF0OUlUUm9uRnNsYUw3SXpublRSMkhvUFZMQzFXVVBEbUxMazdw?= =?utf-8?B?RVBTalBaOGtQT3NYWVRWTks5RXYxSlF2Y2tkeXQwZjdOdmdRdUh5cGVZWitm?= =?utf-8?B?RW92Umw1eDNURnQ1RlltRDRsdkpxeWpPYlY1eERWZjkvcGdRb01sb05UZDBV?= =?utf-8?B?N0kvcFdzUE1QQmpGSE1wUW1jU0ZQbWVrQVM4cTN6eERsRmNZcVpWOHIwN2pH?= =?utf-8?B?ZnV5YWJUWTBySlpEcmJ0SVVQcjE4cExkSDBqYVlrUlNhV0w5TnBZWFptekdW?= =?utf-8?B?SFkvZ0RObEZGUmlrblRkYXcxUUhCWE82NUZha3VLMnIzV3dnbjNDMlFHOVgx?= =?utf-8?B?MzF1N3NORDlvOUNEZUpydXM4cHFDS0dpNktURXZjeHNHZ3JMQnM0aGtMbDJS?= =?utf-8?B?OW8rdWlBUVdrcmNTNkFKMTc4MlkyNFhrR3dxNzdQTHNzQ3RBSnUxcCtCYmw5?= =?utf-8?B?QWpHUTMxQk5XOUdYQVhrWnE0WWIwcTMrTzFqOEFxcVEwNHdIQTVyK2R6aGFE?= =?utf-8?B?Rkp5VkhoNHhWanlJQndmbnJsZnNWOFNoTVBsaE9hajY5MS96WHpCelcrcXRy?= =?utf-8?B?emtzOEEydkgxSnJUR2tCS2E3MmdVK3dNbGVkNTNLUTg2bDQycmptbHdmTjBs?= =?utf-8?B?STNvMmwrRllENUlxTlA2ZkE3YWVhZEFBQndEZ3JZaFdLZ1dJZjBmUEZqS1Rt?= =?utf-8?B?elY1QjNOeHZHNDl5WnVhVlY4V2VaTFRJNjB0bE95Sm9TVnBWVlg5TVlGT1Yz?= =?utf-8?B?cm5OTHRQeGJ1dzlNQmo3RENmMGx4cTJjblB5MTBwWVJ6OHo1U09VTkFqNjdG?= =?utf-8?B?Y2Z3aHNtVjVtbFNTSXBjYXF4K0ZkbW5rZmlUZFlQcU9Ea2dVUWxHbEMxQzBj?= =?utf-8?Q?Vd4Q=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1102; 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charset="us-ascii"; Format="flowed" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org On 10/22/2025 7:35 PM, Shawn Lin wrote: > EXTERNAL EMAIL > > The driver should set app_clk_req_n(clkreq ready) of PCIE_CLIENT_POWER reg > to support L1sub. Otherwise, unset app_clk_req_n and pull down CLKREQ#. > > Signed-off-by: Shawn Lin > > --- > > Changes in v2: > - drop of_pci_clkreq_presnt API > - drop dependency of Niklas's patch > > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 36 +++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > index 3e2752c..18cd626 100644 > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > @@ -62,6 +62,12 @@ > /* Interrupt Mask Register Related to Miscellaneous Operation */ > #define PCIE_CLIENT_INTR_MASK_MISC 0x24 > > +/* Power Management Control Register */ > +#define PCIE_CLIENT_POWER 0x2c > +#define PCIE_CLKREQ_READY 0x10001 > +#define PCIE_CLKREQ_NOT_READY 0x10000 > +#define PCIE_CLKREQ_PULL_DOWN 0x30001000 > + > /* Hot Reset Control Register */ > #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 > #define PCIE_LTSSM_APP_DLY2_EN BIT(1) > @@ -85,6 +91,7 @@ struct rockchip_pcie { > struct regulator *vpcie3v3; > struct irq_domain *irq_domain; > const struct rockchip_pcie_of_data *data; > + bool supports_clkreq; > }; > > struct rockchip_pcie_of_data { > @@ -200,6 +207,31 @@ static bool rockchip_pcie_link_up(struct dw_pcie *pci) > return FIELD_GET(PCIE_LINKUP_MASK, val) == PCIE_LINKUP; > } > > +static void rockchip_pcie_enable_l1sub(struct dw_pcie *pci) > +{ > + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); > + u32 cap, l1subcap; > + > + /* Enable L1 substates if CLKREQ# is properly connected */ > + if (rockchip->supports_clkreq) { > + /* Ready to have reference clock removed */ > + rockchip_pcie_writel_apb(rockchip, PCIE_CLKREQ_READY, PCIE_CLIENT_POWER); > + return; > + } > + > + /* Otherwise, pull down CLKREQ# and disable L1 substates */ > + rockchip_pcie_writel_apb(rockchip, PCIE_CLKREQ_PULL_DOWN | PCIE_CLKREQ_NOT_READY, > + PCIE_CLIENT_POWER); > + cap = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); > + if (cap) { > + l1subcap = dw_pcie_readl_dbi(pci, cap + PCI_L1SS_CAP); > + l1subcap &= ~(PCI_L1SS_CAP_L1_PM_SS | PCI_L1SS_CAP_ASPM_L1_1 | > + PCI_L1SS_CAP_ASPM_L1_2 | PCI_L1SS_CAP_PCIPM_L1_1 | > + PCI_L1SS_CAP_PCIPM_L1_2); > + dw_pcie_writel_dbi(pci, cap + PCI_L1SS_CAP, l1subcap); > + } > +} > + > static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) > { > u32 cap, lnkcap; > @@ -264,6 +296,7 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) > irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler, > rockchip); > > + rockchip_pcie_enable_l1sub(pci); > rockchip_pcie_enable_l0s(pci); > > return 0; > @@ -301,6 +334,7 @@ static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep) > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > enum pci_barno bar; > > + rockchip_pcie_enable_l1sub(pci); > rockchip_pcie_enable_l0s(pci); > rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep); > > @@ -412,6 +446,8 @@ static int rockchip_pcie_resource_get(struct platform_device *pdev, > return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst), > "failed to get reset lines\n"); > > + rockchip->supports_clkreq = of_property_read_bool(pdev->dev.of_node, "supports-clkreq"); Hi Shawn, This line exceeds 80 characters. Can it be like this? rockchip->supports_clkreq = of_property_read_bool(pdev->dev.of_node, "supports-clkreq"); I have no doubts about the rest. Reviewed-by: Hans Zhang Best regards, Hans > + > return 0; > } > > -- > 2.7.4 > > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip