From: "Diederik de Haas" <didi.debian@cknow.org>
To: 李维豪 <cn.liweihao@gmail.com>, "Krzysztof Kozlowski" <krzk@kernel.org>
Cc: <heiko@sntech.de>, <robh@kernel.org>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-rockchip@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC
Date: Sat, 06 Sep 2025 15:57:55 +0200 [thread overview]
Message-ID: <DCLRQQH0F49Q.2OUP59P4VV91O@cknow.org> (raw)
In-Reply-To: <CAPEOAkSpEzVtUqyUJQbDmbmPOjORnAfuehhvo1qqZgAAeY=ZVA@mail.gmail.com>
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On Sat Sep 6, 2025 at 3:34 PM CEST, 李维豪 wrote:
> Krzysztof Kozlowski <krzk@kernel.org> 于2025年9月6日周六 15:21写道:
>> On 06/09/2025 03:34, 李维豪 wrote:
>> > Krzysztof Kozlowski <krzk@kernel.org> 于2025年9月5日周五 22:13写道:
>> >> On 05/09/2025 15:23, WeiHao Li wrote:
>> >>> We need a clock id to assign clock parent when use i2s 8ch as audio
>> >>> device, CLK_I2S_8CH_FRAC should be CLK_I2S_8CH_PRE parent so we can get
>> >>> frequency we want.
>> >>>
>> >>> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
>> >>> ---
>> >>> include/dt-bindings/clock/rk3368-cru.h | 3 +++
>> >>> 1 file changed, 3 insertions(+)
>> >>>
>> >>> diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
>> >>> index b951e29069..795e721957 100644
>> >>> --- a/include/dt-bindings/clock/rk3368-cru.h
>> >>> +++ b/include/dt-bindings/clock/rk3368-cru.h
>> >>> @@ -183,6 +183,9 @@
>> >>> #define HCLK_BUS 477
>> >>> #define HCLK_PERI 478
>> >>>
>> >>> +#define CLK_I2S_8CH_PRE 500
>> >>
>> >> 479
>> >>
>> >>> +#define CLK_I2S_8CH_FRAC 501
>> >>
>> >> 480, no?
>> >>
>> >
>> > Neither of these clocks belong to the previous grouping in terms of
>> > type, so I chose to start with a new integer id here.
>>
>> I don't know what is "previous grouping" here, but IDs are abstract and
>> are incremented by 1.
>
> In the current kernel code, the RK3368 clock IDs are categorized by
> SCLK, ACLK, PCLK, and HCLK.
Maybe this helps understanding the discrepancy:
Starting with the rk3588 series, clock IDs are in the 'clock' binding
dir and named "rockchip,rk<SoC-id>-cru.h" and are numbered sequentially
with no gaps. And the reset IDs are in the 'reset' binding dir with the
same filename pattern.
With older SoC series, including rk3568*, both the clock and reset IDs
are in "clock/rk<SoC-id>-cru.h" where they are NOT sequentially
numbered and thus jumps in the numbering is not out of place there.
HTH,
Diederik
*) I have a local commit which moves the reset IDs to
"reset/rockchip,rk3568-cru.h", but I don't know how to do/fix the
numbering, so I never submitted it.
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next prev parent reply other threads:[~2025-09-06 14:07 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-05 13:23 [PATCH v1 0/4] clk/rockchip: Fix I2S 8CH mclk output for RK3368 WeiHao Li
2025-09-05 13:23 ` [PATCH v1 1/4] clk: rockchip: rk3368: fix SCLK_I2S_8CH_OUT flags WeiHao Li
2025-09-05 13:23 ` [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC WeiHao Li
2025-09-05 14:13 ` Krzysztof Kozlowski
2025-09-06 1:34 ` 李维豪
2025-09-06 7:21 ` Krzysztof Kozlowski
2025-09-06 13:34 ` 李维豪
2025-09-06 13:57 ` Diederik de Haas [this message]
2025-09-05 13:23 ` [PATCH v1 3/4] clk: rockchip: rk3368: use clock ids " WeiHao Li
2025-09-05 13:23 ` [PATCH v1 4/4] arm64: dts: rockchip: Assign I2S 8 channel clock for rk3368 WeiHao Li
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