Re: [PATCH] PCI: dw-rockchip: Skip waiting for link up

From: "Diederik de Haas" <diederik@cknow-tech.com>
To: "Niklas Cassel" <cassel@kernel.org>,
	"Shawn Lin" <shawn.lin@rock-chips.com>
Cc: "FUKAUMI Naoki" <naoki@radxa.com>,
	"Damien Le Moal" <dlemoal@kernel.org>,
	"Anand Moon" <linux.amoon@gmail.com>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
	"Dragan Simic" <dsimic@manjaro.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>
Subject: Re: [PATCH] PCI: dw-rockchip: Skip waiting for link up
Date: Sat, 08 Nov 2025 15:21:45 +0100	[thread overview]
Message-ID: <DE3DPAVIOGZP.7RW4SGB8HXUT@cknow-tech.com> (raw)
In-Reply-To: <aQ9FWEuW47L8YOxC@ryzen>

On Sat Nov 8, 2025 at 2:27 PM CET, Niklas Cassel wrote:
> On Sat, Nov 08, 2025 at 01:34:32PM +0100, Niklas Cassel wrote:
>> 
>> The pcie-dw-rockchip.c driver is modelled after the qcom driver.
>> So if this is a problem when a ASM2806 switch is connected, I would
>> expect qcom platforms to have the same problem.
>
> Looking more closely at this, comparing the "good" kernel:

There's another thing that caught my eye ...

> [    1.868857] pci 0004:40:00.0: [1d87:3588] type 01 class 0x060400 PCIe Root Port
> [    1.869509] pci 0004:40:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> ...
> [    1.879764] pci 0004:41:00.0: enabling Extended Tags
> [    1.880614] pci 0004:41:00.0: PME# supported from D0 D3hot D3cold
> [    1.881409] pci 0004:41:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x1 link at 0004:40:00.0 (capable of 15.752 Gb/s with 8.0 GT/s PCIe x2 link)

... 2.000 Gb/s ...

> [    1.888729] pci 0004:41:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> ...
>
>
> With the "bad" kernel:
> [    1.383075] pci 0004:40:00.0: [1d87:3588] type 01 class 0x060400 PCIe Root Port
> [    1.383738] pci 0004:40:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> ...
> [    1.415746] pci 0004:41:00.0: enabling Extended Tags
> [    1.416465] pci 0004:41:00.0: PME# supported from D0 D3hot D3cold
> [    1.417181] pci 0004:41:00.0: 4.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x1 link at 0004:40:00.0 (capable of 15.752 Gb/s with 8.0 GT/s PCIe x2 link)

... 4.0000 Gb/s

I don't know if that's relevant or important, but wanted to mention it.

Cheers,
  Diederik

> [    1.423384] pci 0004:41:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> ...
>
>
> We can see that the pcie-dw-rockchip.c driver detects the ASM2806 switch
> in both cases. So the problem is not really with enumerating the root port.
>
> The problem seems to be that with the "bad" kernel, you get a lot of:
> [    1.464651] pci 0004:42:00.0: devices behind bridge are unusable because [bus 43] cannot be assigned for them
>
> Because the bus ends are different, and conflicts with each other.
> I don't know why this happens.
>
> Perhaps we could add a quirk for ASM2806 that does some extra sleep if that
> switch is detected, if for some reason, the switch is not actually ready
> after the delays defined by the PCIe specification.
>
> (And btw. please test with the latest 6.18-rc, as, from experience, the
> ASPM problems in earlier RCs can result in some weird problems that are
> not immediately deduced to be caused by the ASPM enablement.)
>
>
> Kind regards,
> Niklas

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