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From: "Diederik de Haas" To: "Heiko Stuebner" Cc: , , , , , , References: <20260312213019.13965-1-heiko@sntech.de> <20260312213019.13965-3-heiko@sntech.de> In-Reply-To: X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260316_092238_556466_139A670E X-CRM114-Status: GOOD ( 11.64 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Hi Heiko, On Thu Mar 12, 2026 at 10:30 PM CET, Heiko Stuebner wrote: > Enable the One Time Programmable Controller (OTPC) in RK356x and add > an initial nvmem fixed layout. I build a kernel with the nvmem patches and your patches from this series and tried it out on my NanoPi R5S with a RK3568 SoC. Navigating to ``/sys/bus/nvmem/devices/rockchip-otp0/cells`` and then doing ``hexdump `` showed all kind of values. Then I did the same with my PineNote with a RK3566 SoC and that gave different values, except for npu-leakage, which I guess is fine? So feel free to include my Tested-by: Diederik de Haas # NanoPi R5S, PineNote Cheers, Diederik > Signed-off-by: Heiko Stuebner > --- > arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi > index 68b48606f601..c8321af7de7d 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi > @@ -1123,6 +1123,52 @@ rng: rng@fe388000 { > status = "disabled"; > }; > > + otp: efuse@fe38c000 { > + compatible = "rockchip,rk3568-otp"; > + reg = <0x0 0xfe38c000 0x0 0x4000>; > + clocks = <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>, > + <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>; > + clock-names = "otp", "apb_pclk", "phy", "sbpi"; > + resets = <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>, > + <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>; > + reset-names = "otp", "apb", "phy", "sbpi"; > + > + nvmem-layout { > + compatible = "fixed-layout"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpu_code: cpu-code@2 { > + reg = <0x02 0x2>; > + }; > + > + otp_cpu_version: cpu-version@8 { > + reg = <0x08 0x1>; > + bits = <3 3>; > + }; > + > + otp_id: id@a { > + reg = <0x0a 0x10>; > + }; > + > + cpu_leakage: cpu-leakage@1a { > + reg = <0x1a 0x1>; > + }; > + > + log_leakage: log-leakage@1b { > + reg = <0x1b 0x1>; > + }; > + > + npu_leakage: npu-leakage@1c { > + reg = <0x1c 0x1>; > + }; > + > + gpu_leakage: gpu-leakage@1d { > + reg = <0x1d 0x1>; > + }; > + }; > + }; > + > i2s0_8ch: i2s@fe400000 { > compatible = "rockchip,rk3568-i2s-tdm"; > reg = <0x0 0xfe400000 0x0 0x1000>; _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip