From: "Diederik de Haas" <diederik@cknow-tech.com>
To: "Cristian Ciocaltea" <cristian.ciocaltea@collabora.com>,
"Diederik de Haas" <diederik@cknow-tech.com>,
"Sandy Huang" <hjc@rock-chips.com>,
"Heiko Stübner" <heiko@sntech.de>,
"Andy Yan" <andy.yan@rock-chips.com>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Andrzej Hajda" <andrzej.hajda@intel.com>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Robert Foss" <rfoss@kernel.org>,
"Laurent Pinchart" <Laurent.pinchart@ideasonboard.com>,
"Jonas Karlman" <jonas@kwiboo.se>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Luca Ceresoli" <luca.ceresoli@bootlin.com>
Cc: <kernel@collabora.com>, "Andy Yan" <andyshrk@163.com>,
<dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-rockchip@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/9] drm/rockchip: vop2: Reset AXI and DCLK to improve robustness
Date: Mon, 06 Jul 2026 00:20:13 +0200 [thread overview]
Message-ID: <DJQZJUFLM425.2J87266L7CGT8@cknow-tech.com> (raw)
In-Reply-To: <c8242f5c-ec74-489e-b378-f225ec3a0135@collabora.com>
Hi Cristian,
On Sun Jul 5, 2026 at 10:46 PM CEST, Cristian Ciocaltea wrote:
> On 7/5/26 4:28 PM, Diederik de Haas wrote:
>> On Wed Jun 17, 2026 at 8:52 PM CEST, Cristian Ciocaltea wrote:
>>> Assert the AXI reset in the CRTC disable path, and the VP DCLK reset in
>>> the enable path.
>>>
>>> These resets are intended to leave the hardware in a clean state for the
>>> next use, helping recover from exceptions such as IOMMU page faults, as
>>> well as to prevent random display output glitches, such as a blank
>>> image, observed when switching modes that also change the color format,
>>> e.g. from RGB to YUV420 and vice versa.
>>>
>>> For now this seems to affect only the RK3588, hence the resets are
>>> optional and will be provided in the device tree for this SoC only.
>>
>> Why do you think it only effect RK3588?
>
> My findings are exclusively in the context of validating YUV support for DW HDMI
> QP, hence targeting RK3588 and RK3576. Since RK3576 didn't exhibit any
> anomalies, I concluded the resets are needed just for RK3588.
Ok, that's indeed a different technology stack.
>> I reported about my RK3568 test here:
>> https://lore.kernel.org/linux-rockchip/DFRU6ODDM71P.3NQGLRK8IVDUY@cknow-tech.com/
>> "I then went on to try LibreELEC's builds. The artifacts I (sometimes)
>> saw, were gone :-D OTOH, I did get several major issues 'in return',
>> like rk_iommu Page fault resulting in a black screen and the only way to
>> 'recover' from it, was a reboot."
>>
>> And I reported some more test results here:
>> https://forum.libreelec.tv/thread/29953-le13-testing-for-rk3288-rk3328-rk3399-rk3566-rk3568-rk3576-rk3588/?postID=204691#post204691
>>
>> That seems to me a (strong) indication it also affects RK3566/RK3568?
>
> If coincidentally this helps improve the reliability of some of the older SoCs
> as well, the resets can easily be added to the corresponding DTs and submitted
> as a follow-up series.
Agreed. Thanks :)
Cheers,
Diederik
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next prev parent reply other threads:[~2026-07-05 22:20 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-17 18:51 [PATCH 0/9] Support 10-bit YUV422 and 8/10-bit YUV420 color format on DW HDMI QP Cristian Ciocaltea
2026-06-17 18:51 ` [PATCH 1/9] dt-bindings: display: vop2: Add missing reset properties Cristian Ciocaltea
2026-06-18 7:58 ` Diederik de Haas
2026-06-18 8:39 ` Cristian Ciocaltea
2026-07-03 16:37 ` Heiko Stübner
2026-07-03 16:59 ` Cristian Ciocaltea
2026-06-22 13:25 ` Krzysztof Kozlowski
2026-06-17 18:51 ` [PATCH 2/9] drm/rockchip: vop2: Reset AXI and DCLK to improve robustness Cristian Ciocaltea
2026-06-18 9:39 ` Philipp Zabel
2026-06-18 11:46 ` Cristian Ciocaltea
2026-06-18 11:52 ` Philipp Zabel
2026-07-05 13:28 ` Diederik de Haas
2026-07-05 20:46 ` Cristian Ciocaltea
2026-07-05 22:20 ` Diederik de Haas [this message]
2026-06-17 18:51 ` [PATCH 3/9] drm/rockchip: vop2: Avoid DCLK source switch for 10-bit YUV422 output Cristian Ciocaltea
2026-06-17 18:51 ` [PATCH 4/9] drm/rockchip: vop2: Consolidate HDMI PHY PLL clock parent switch Cristian Ciocaltea
2026-06-17 18:51 ` [PATCH 5/9] drm/rockchip: vop2: Switch to enum vop_csc_format Cristian Ciocaltea
2026-06-17 18:51 ` [PATCH 6/9] drm/bridge: dw-hdmi-qp: Log resolution and refresh rate in atomic_enable() Cristian Ciocaltea
2026-06-17 18:52 ` [PATCH 7/9] drm/rockchip: dw_hdmi_qp: Support 10-bit YUV422 output format Cristian Ciocaltea
2026-06-17 18:52 ` [PATCH 8/9] drm/rockchip: dw_hdmi_qp: Enable YUV420 " Cristian Ciocaltea
2026-06-17 18:52 ` [PATCH 9/9] arm64: dts: rockchip: Add RK3588 VOP2 resets Cristian Ciocaltea
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