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Thu, 10 Dec 2020 09:48:31 -0800 (PST) Date: Thu, 10 Dec 2020 18:48:30 +0100 From: Thierry Reding To: Simon South Subject: Re: [PATCH] pwm: rockchip: Eliminate potential race condition when probing Message-ID: References: <875z5nof46.fsf@simonsouth.net> <20201130004419.1714-1-simon@simonsouth.net> MIME-Version: 1.0 In-Reply-To: <20201130004419.1714-1-simon@simonsouth.net> User-Agent: Mutt/2.0.3 (a51f058f) (2020-12-04) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201210_124834_209609_D9913190 X-CRM114-Status: GOOD ( 26.74 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, heiko@sntech.de, bbrezillon@kernel.org, linux-rockchip@lists.infradead.org, u.kleine-koenig@pengutronix.de, tpiepho@gmail.com, lee.jones@linaro.org, linux-arm-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============1763101167377241085==" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org --===============1763101167377241085== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="gaMZ9YjfFCQG1Hdo" Content-Disposition: inline --gaMZ9YjfFCQG1Hdo Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Nov 29, 2020 at 07:44:19PM -0500, Simon South wrote: > Commit 48cf973cae33 ("pwm: rockchip: Avoid glitches on already running > PWMs") introduced a potential race condition in rockchip_pwm_probe() by > having it disable the clock of a PWM already registered through a call to > pwmchip_add(). >=20 > Eliminate this possibility by calling clk_enable() for a probed PWM's clo= ck > only when it appears the PWM itself has already been enabled (by a > bootloader, presumably), instead of always enabling the clock and then > disabling it after registration for non-enabled PWMs. >=20 > Fixes: 48cf973cae33 ("pwm: rockchip: Avoid glitches on already running PW= Ms") > Fixes: 457f74abbed0 ("pwm: rockchip: Keep enabled PWMs running while prob= ing") > Reported-by: Trent Piepho > Signed-off-by: Simon South > --- > drivers/pwm/pwm-rockchip.c | 45 ++++++++++++++++++++++++++------------ > 1 file changed, 31 insertions(+), 14 deletions(-) >=20 > diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c > index 77c23a2c6d71..7efba1d0adb4 100644 > --- a/drivers/pwm/pwm-rockchip.c > +++ b/drivers/pwm/pwm-rockchip.c > @@ -289,6 +289,7 @@ static int rockchip_pwm_probe(struct platform_device = *pdev) > struct rockchip_pwm_chip *pc; > struct resource *r; > u32 enable_conf, ctrl; > + bool enabled; > int ret, count; > =20 > id =3D of_match_device(rockchip_pwm_dt_ids, &pdev->dev); > @@ -299,6 +300,8 @@ static int rockchip_pwm_probe(struct platform_device = *pdev) > if (!pc) > return -ENOMEM; > =20 > + pc->data =3D id->data; > + > r =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); > pc->base =3D devm_ioremap_resource(&pdev->dev, r); > if (IS_ERR(pc->base)) > @@ -326,21 +329,38 @@ static int rockchip_pwm_probe(struct platform_devic= e *pdev) > return ret; > } > =20 > - ret =3D clk_prepare_enable(pc->clk); > + ret =3D clk_prepare(pc->clk); > if (ret) { > - dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret); > + dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret); > return ret; > } > =20 > + /* > + * If it appears the PWM has already been enabled, perhaps by a > + * bootloader, re-enable its clock to increment the clock's enable > + * counter and ensure it is kept running (particularly in the case > + * where there is no separate APB clock). > + */ > + enable_conf =3D pc->data->enable_conf; > + ctrl =3D readl_relaxed(pc->base + pc->data->regs.ctrl); > + enabled =3D (ctrl & enable_conf) =3D=3D enable_conf; Given that we don't enable the bus clock before this, is it even safe to access registers on the bus if the clock is disabled? I've seen a lot of cases where accesses to an unclocked bus either lead to silent hangs or very noisy crashes, and I would expect something like that (or something in between) to happen on Rockchip SoCs. Have you tested this for cases where the bus clock is initially disabled? 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