From: Ricardo Ribalda <ribalda@chromium.org>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-media@vger.kernel.org,
Dafna Hirschfeld <dafna@fastmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Paul Elder <paul.elder@ideasonboard.com>,
Tomasz Figa <tfiga@google.com>,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v4 09/21] media: rkisp1: regs: Rename CCL, ICCL and IRCL registers with VI_ prefix
Date: Mon, 25 Apr 2022 11:51:53 +0200 [thread overview]
Message-ID: <YmZvOXPfxZ7UYPhw@gmail.com> (raw)
In-Reply-To: <20220421234240.1694-10-laurent.pinchart@ideasonboard.com>
Laurent Pinchart wrote:
> The documentation names the CCL, ICCL and IRCL registers with a VI_
> prefix, like the VI_ID and VI_DPCL registers. Fix the macro names
> accordingly.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Reviewed-by: Dafna Hirschfeld <dafna@fastmail.com>
Reviewed-by: Ricardo Ribalda <ribalda@chromium.org>
> ---
> .../platform/rockchip/rkisp1/rkisp1-isp.c | 19 +++---
> .../platform/rockchip/rkisp1/rkisp1-params.c | 8 +--
> .../platform/rockchip/rkisp1/rkisp1-regs.h | 60 +++++++++----------
> 3 files changed, 44 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> index 4f7b2157b8cc..3c77cec568fb 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> @@ -523,20 +523,21 @@ static void rkisp1_isp_stop(struct rkisp1_device *rkisp1)
> readx_poll_timeout(readl, rkisp1->base_addr + RKISP1_CIF_ISP_RIS,
> val, val & RKISP1_CIF_ISP_OFF, 20, 100);
> rkisp1_write(rkisp1,
> - RKISP1_CIF_IRCL_MIPI_SW_RST | RKISP1_CIF_IRCL_ISP_SW_RST,
> - RKISP1_CIF_IRCL);
> - rkisp1_write(rkisp1, 0x0, RKISP1_CIF_IRCL);
> + RKISP1_CIF_VI_IRCL_MIPI_SW_RST |
> + RKISP1_CIF_VI_IRCL_ISP_SW_RST,
> + RKISP1_CIF_VI_IRCL);
> + rkisp1_write(rkisp1, 0x0, RKISP1_CIF_VI_IRCL);
> }
>
> static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
> {
> - u32 val = RKISP1_CIF_ICCL_ISP_CLK | RKISP1_CIF_ICCL_CP_CLK |
> - RKISP1_CIF_ICCL_MRSZ_CLK | RKISP1_CIF_ICCL_SRSZ_CLK |
> - RKISP1_CIF_ICCL_JPEG_CLK | RKISP1_CIF_ICCL_MI_CLK |
> - RKISP1_CIF_ICCL_IE_CLK | RKISP1_CIF_ICCL_MIPI_CLK |
> - RKISP1_CIF_ICCL_DCROP_CLK;
> + u32 val = RKISP1_CIF_VI_ICCL_ISP_CLK | RKISP1_CIF_VI_ICCL_CP_CLK |
> + RKISP1_CIF_VI_ICCL_MRSZ_CLK | RKISP1_CIF_VI_ICCL_SRSZ_CLK |
> + RKISP1_CIF_VI_ICCL_JPEG_CLK | RKISP1_CIF_VI_ICCL_MI_CLK |
> + RKISP1_CIF_VI_ICCL_IE_CLK | RKISP1_CIF_VI_ICCL_MIPI_CLK |
> + RKISP1_CIF_VI_ICCL_DCROP_CLK;
>
> - rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL);
> + rkisp1_write(rkisp1, val, RKISP1_CIF_VI_ICCL);
>
> /* ensure sp and mp can run at the same time in V12 */
> if (rkisp1->media_dev.hw_revision == RKISP1_V12) {
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> index f6da2571b55f..cb5840b5d974 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> @@ -1058,8 +1058,8 @@ static void rkisp1_ie_config(struct rkisp1_params *params,
> static void rkisp1_ie_enable(struct rkisp1_params *params, bool en)
> {
> if (en) {
> - rkisp1_param_set_bits(params, RKISP1_CIF_ICCL,
> - RKISP1_CIF_ICCL_IE_CLK);
> + rkisp1_param_set_bits(params, RKISP1_CIF_VI_ICCL,
> + RKISP1_CIF_VI_ICCL_IE_CLK);
> rkisp1_write(params->rkisp1, RKISP1_CIF_IMG_EFF_CTRL_ENABLE,
> RKISP1_CIF_IMG_EFF_CTRL);
> rkisp1_param_set_bits(params, RKISP1_CIF_IMG_EFF_CTRL,
> @@ -1067,8 +1067,8 @@ static void rkisp1_ie_enable(struct rkisp1_params *params, bool en)
> } else {
> rkisp1_param_clear_bits(params, RKISP1_CIF_IMG_EFF_CTRL,
> RKISP1_CIF_IMG_EFF_CTRL_ENABLE);
> - rkisp1_param_clear_bits(params, RKISP1_CIF_ICCL,
> - RKISP1_CIF_ICCL_IE_CLK);
> + rkisp1_param_clear_bits(params, RKISP1_CIF_VI_ICCL,
> + RKISP1_CIF_VI_ICCL_IE_CLK);
> }
> }
>
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> index 887f4768dc0a..0f6ea67b4d5a 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> @@ -210,7 +210,7 @@
> #define RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP BIT(1)
> #define RKISP1_CIF_MI_XTD_FMT_CTRL_DMA_CB_CR_SWAP BIT(2)
>
> -/* CCL */
> +/* VI_CCL */
> #define RKISP1_CIF_CCL_CIF_CLK_DIS BIT(2)
> /* VI_ISP_CLK_CTRL */
> #define RKISP1_CIF_CLK_CTRL_ISP_RAW BIT(0)
> @@ -241,32 +241,32 @@
> #define RKISP1_CIF_CLK_CTRL_RSZS BIT(25)
> #define RKISP1_CIF_CLK_CTRL_MIPI BIT(26)
> #define RKISP1_CIF_CLK_CTRL_MARVINMI BIT(27)
> -/* ICCL */
> -#define RKISP1_CIF_ICCL_ISP_CLK BIT(0)
> -#define RKISP1_CIF_ICCL_CP_CLK BIT(1)
> -#define RKISP1_CIF_ICCL_RES_2 BIT(2)
> -#define RKISP1_CIF_ICCL_MRSZ_CLK BIT(3)
> -#define RKISP1_CIF_ICCL_SRSZ_CLK BIT(4)
> -#define RKISP1_CIF_ICCL_JPEG_CLK BIT(5)
> -#define RKISP1_CIF_ICCL_MI_CLK BIT(6)
> -#define RKISP1_CIF_ICCL_RES_7 BIT(7)
> -#define RKISP1_CIF_ICCL_IE_CLK BIT(8)
> -#define RKISP1_CIF_ICCL_SIMP_CLK BIT(9)
> -#define RKISP1_CIF_ICCL_SMIA_CLK BIT(10)
> -#define RKISP1_CIF_ICCL_MIPI_CLK BIT(11)
> -#define RKISP1_CIF_ICCL_DCROP_CLK BIT(12)
> -/* IRCL */
> -#define RKISP1_CIF_IRCL_ISP_SW_RST BIT(0)
> -#define RKISP1_CIF_IRCL_CP_SW_RST BIT(1)
> -#define RKISP1_CIF_IRCL_YCS_SW_RST BIT(2)
> -#define RKISP1_CIF_IRCL_MRSZ_SW_RST BIT(3)
> -#define RKISP1_CIF_IRCL_SRSZ_SW_RST BIT(4)
> -#define RKISP1_CIF_IRCL_JPEG_SW_RST BIT(5)
> -#define RKISP1_CIF_IRCL_MI_SW_RST BIT(6)
> -#define RKISP1_CIF_IRCL_CIF_SW_RST BIT(7)
> -#define RKISP1_CIF_IRCL_IE_SW_RST BIT(8)
> -#define RKISP1_CIF_IRCL_SI_SW_RST BIT(9)
> -#define RKISP1_CIF_IRCL_MIPI_SW_RST BIT(11)
> +/* VI_ICCL */
> +#define RKISP1_CIF_VI_ICCL_ISP_CLK BIT(0)
> +#define RKISP1_CIF_VI_ICCL_CP_CLK BIT(1)
> +#define RKISP1_CIF_VI_ICCL_RES_2 BIT(2)
> +#define RKISP1_CIF_VI_ICCL_MRSZ_CLK BIT(3)
> +#define RKISP1_CIF_VI_ICCL_SRSZ_CLK BIT(4)
> +#define RKISP1_CIF_VI_ICCL_JPEG_CLK BIT(5)
> +#define RKISP1_CIF_VI_ICCL_MI_CLK BIT(6)
> +#define RKISP1_CIF_VI_ICCL_RES_7 BIT(7)
> +#define RKISP1_CIF_VI_ICCL_IE_CLK BIT(8)
> +#define RKISP1_CIF_VI_ICCL_SIMP_CLK BIT(9)
> +#define RKISP1_CIF_VI_ICCL_SMIA_CLK BIT(10)
> +#define RKISP1_CIF_VI_ICCL_MIPI_CLK BIT(11)
> +#define RKISP1_CIF_VI_ICCL_DCROP_CLK BIT(12)
> +/* VI_IRCL */
> +#define RKISP1_CIF_VI_IRCL_ISP_SW_RST BIT(0)
> +#define RKISP1_CIF_VI_IRCL_CP_SW_RST BIT(1)
> +#define RKISP1_CIF_VI_IRCL_YCS_SW_RST BIT(2)
> +#define RKISP1_CIF_VI_IRCL_MRSZ_SW_RST BIT(3)
> +#define RKISP1_CIF_VI_IRCL_SRSZ_SW_RST BIT(4)
> +#define RKISP1_CIF_VI_IRCL_JPEG_SW_RST BIT(5)
> +#define RKISP1_CIF_VI_IRCL_MI_SW_RST BIT(6)
> +#define RKISP1_CIF_VI_IRCL_CIF_SW_RST BIT(7)
> +#define RKISP1_CIF_VI_IRCL_IE_SW_RST BIT(8)
> +#define RKISP1_CIF_VI_IRCL_SI_SW_RST BIT(9)
> +#define RKISP1_CIF_VI_IRCL_MIPI_SW_RST BIT(11)
>
> /* C_PROC_CTR */
> #define RKISP1_CIF_C_PROC_CTR_ENABLE BIT(0)
> @@ -687,11 +687,11 @@
> /* CIF Registers */
> /* =================================================================== */
> #define RKISP1_CIF_CTRL_BASE 0x00000000
> -#define RKISP1_CIF_CCL (RKISP1_CIF_CTRL_BASE + 0x00000000)
> +#define RKISP1_CIF_VI_CCL (RKISP1_CIF_CTRL_BASE + 0x00000000)
> #define RKISP1_CIF_VI_ID (RKISP1_CIF_CTRL_BASE + 0x00000008)
> #define RKISP1_CIF_VI_ISP_CLK_CTRL_V12 (RKISP1_CIF_CTRL_BASE + 0x0000000C)
> -#define RKISP1_CIF_ICCL (RKISP1_CIF_CTRL_BASE + 0x00000010)
> -#define RKISP1_CIF_IRCL (RKISP1_CIF_CTRL_BASE + 0x00000014)
> +#define RKISP1_CIF_VI_ICCL (RKISP1_CIF_CTRL_BASE + 0x00000010)
> +#define RKISP1_CIF_VI_IRCL (RKISP1_CIF_CTRL_BASE + 0x00000014)
> #define RKISP1_CIF_VI_DPCL (RKISP1_CIF_CTRL_BASE + 0x00000018)
>
> #define RKISP1_CIF_IMG_EFF_BASE 0x00000200
> --
> Regards,
>
> Laurent Pinchart
>
>
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next prev parent reply other threads:[~2022-04-25 9:52 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-21 23:42 [PATCH v4 00/21] media: rkisp1: Misc bug fixes and cleanups Laurent Pinchart
2022-04-21 23:42 ` [PATCH v4 01/21] media: rkisp1: capture: Initialize entity before video device Laurent Pinchart
2022-04-25 7:52 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 02/21] media: rkisp1: capture: Fix and simplify (un)registration Laurent Pinchart
2022-04-25 9:34 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 03/21] media: rkisp1: isp: " Laurent Pinchart
2022-04-25 9:36 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 04/21] media: rkisp1: resizer: " Laurent Pinchart
2022-04-25 9:37 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 05/21] media: rkisp1: params: " Laurent Pinchart
2022-04-25 9:39 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 06/21] media: rkisp1: stats: Simplify (un)registration Laurent Pinchart
2022-04-25 9:44 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 07/21] media: rkisp1: Simplify rkisp1_entities_register() error path Laurent Pinchart
2022-04-25 9:45 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 08/21] media: rkisp1: regs: Don't use BIT() macro for multi-bit register fields Laurent Pinchart
2022-04-25 9:50 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 09/21] media: rkisp1: regs: Rename CCL, ICCL and IRCL registers with VI_ prefix Laurent Pinchart
2022-04-25 9:51 ` Ricardo Ribalda [this message]
2022-04-21 23:42 ` [PATCH v4 10/21] media: rkisp1: Swap value and address arguments to rkisp1_write() Laurent Pinchart
2022-04-25 9:53 ` Ricardo Ribalda
2022-04-25 18:59 ` Laurent Pinchart
2022-04-21 23:42 ` [PATCH v4 11/21] media: rkisp1: resizer: Simplify register access Laurent Pinchart
2022-04-25 9:58 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 12/21] media: rkisp1: Move debugfs code to a separate file Laurent Pinchart
2022-04-25 10:54 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 13/21] media: rkisp1: Compile debugfs support conditionally Laurent Pinchart
2022-04-25 10:58 ` Ricardo Ribalda
2022-04-25 19:08 ` Laurent Pinchart
2022-04-26 7:33 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 14/21] media: rkisp1: debug: Collect input status by sampling ISP_FLAGS_SHD Laurent Pinchart
2022-04-25 11:08 ` Ricardo Ribalda
2022-04-25 20:13 ` Laurent Pinchart
2022-04-21 23:42 ` [PATCH v4 15/21] media: rkisp1: debug: Add debugfs files to dump core and ISP registers Laurent Pinchart
2022-04-25 11:13 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 16/21] media: rkisp1: debug: Move resizer register dump to debugfs Laurent Pinchart
2022-04-25 11:16 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 17/21] media: rkisp1: debug: Consolidate reg dumps for shadow registers Laurent Pinchart
2022-04-25 11:45 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 18/21] media: rkisp1: debug: Compute max register length name dynamically Laurent Pinchart
2022-04-25 11:49 ` Ricardo Ribalda
2022-04-25 19:05 ` Laurent Pinchart
2022-04-25 21:01 ` [PATCH v4.1 18/21] media: rkisp1: debug: Update max register name length Laurent Pinchart
2022-04-26 7:39 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 19/21] media: rkisp1: capture: Bypass the main device for handling querycap Laurent Pinchart
2022-04-25 11:51 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 20/21] media: rkisp1: Align macro definitions Laurent Pinchart
2022-04-25 11:52 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 21/21] media: rkisp1: Drop parentheses and fix indentation in rkisp1_probe() Laurent Pinchart
2022-04-25 8:30 ` Ricardo Ribalda
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