Re: [PATCH 7/8] arm64: dts: rockchip: Add SDMMC/SDIO controllers for RK3528

Jonas Karlman
2025-03-01T12:49:46Z

Hi,

On 2025-03-01 11:47, Yao Zi wrote:
> RK3528 features two SDIO controllers and one SD/MMC controller, describe
> them in devicetree. Since their sample and drive clocks are located in
> the VO and VPU GRFs, corresponding syscons are added to make these
> clocks available.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> arch/arm64/boot/dts/rockchip/rk3528.dtsi | 62 ++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> index 5b334690356a..078c97fa1d9f 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/clock/rockchip,rk3528-cru.h>
> +#include <dt-bindings/reset/rockchip,rk3528-cru.h>
>
> / {
> compatible = "rockchip,rk3528";
> @@ -122,6 +123,16 @@ gic: interrupt-controller@fed01000 {
> #interrupt-cells = <3>;
> };
>
> + vpu_grf: syscon@ff340000 {
> + compatible = "rockchip,rk3528-vpu-grf", "syscon";

vpu_grf is also used for gmac1, so should possible be a "syscon",
"simple-mfd", or have I misunderstood when to use simple-mfd ?

> + reg = <0x0 0xff340000 0x0 0x8000>;
> + };
> +
> + vo_grf: syscon@ff360000 {
> + compatible = "rockchip,rk3528-vo-grf", "syscon";

similar here, vo_grf is also used for gmac0.

> + reg = <0x0 0xff360000 0x0 0x10000>;
> + };
> +
> cru: clock-controller@ff4a0000 {
> compatible = "rockchip,rk3528-cru";
> reg = <0x0 0xff4a0000 0x0 0x30000>;
> @@ -251,5 +262,56 @@ uart7: serial@ffa28000 {
> reg-shift = <2>;
> status = "disabled";
> };
> +
> + sdio0: mmc@ffc10000 {
> + compatible = "rockchip,rk3528-dw-mshc",
> + "rockchip,rk3288-dw-mshc";
> + reg = <0x0 0xffc10000 0x0 0x4000>;
> + clocks = <&cru HCLK_SDIO0>,
> + <&cru CCLK_SRC_SDIO0>,
> + <&cru SCLK_SDIO0_DRV>,
> + <&cru SCLK_SDIO0_SAMPLE>;
> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
> + max-frequency = <150000000>;
> + resets = <&cru SRST_H_SDIO0>;
> + reset-names = "reset";
> + status = "disabled";
> + };
> +
> + sdio1: mmc@ffc20000 {
> + compatible = "rockchip,rk3528-dw-mshc",
> + "rockchip,rk3288-dw-mshc";
> + reg = <0x0 0xffc20000 0x0 0x4000>;
> + clocks = <&cru HCLK_SDIO1>,
> + <&cru CCLK_SRC_SDIO1>,
> + <&cru SCLK_SDIO1_DRV>,
> + <&cru SCLK_SDIO1_SAMPLE>;
> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + max-frequency = <150000000>;
> + resets = <&cru SRST_H_SDIO1>;
> + reset-names = "reset";
> + status = "disabled";
> + };
> +
> + sdmmc: mmc@ffc30000 {
> + compatible = "rockchip,rk3528-dw-mshc",
> + "rockchip,rk3288-dw-mshc";
> + reg = <0x0 0xffc30000 0x0 0x4000>;
> + clocks = <&cru HCLK_SDMMC0>,
> + <&cru CCLK_SRC_SDMMC0>,
> + <&cru SCLK_SDMMC_DRV>,
> + <&cru SCLK_SDMMC_SAMPLE>;
> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + max-frequency = <150000000>;
> + resets = <&cru SRST_H_SDMMC0>;
> + reset-names = "reset";

Suggest adding default pinctrl props here:

pinctrl-names = "default";
pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_det>;

And possible also for sdio0 and sdio1.

Regards,
Jonas

> + status = "disabled";
> + };
> };
> };