From: Niklas Cassel <cassel@kernel.org>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v2] PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up()
Date: Thu, 10 Apr 2025 08:10:56 +0200 [thread overview]
Message-ID: <Z_dg8GkmQNvJxIJ6@ryzen> (raw)
In-Reply-To: <1744192308-238386-1-git-send-email-shawn.lin@rock-chips.com>
On Wed, Apr 09, 2025 at 05:51:48PM +0800, Shawn Lin wrote:
> Two mistakes here:
> 1. 0x11 is L0 not L0S, so the naming is wrong from the very beginning.
> 2. It's totally broken if enabling ASPM as rockchip_pcie_link_up() treat other
> states, for instance, L0S or L1 as link down which is obviously wrong.
>
> Remove the check.
>
> Fixes: 0e898eb8df4e ("PCI: rockchip-dwc: Add Rockchip RK356X host controller driver")
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
Reviewed-by: Niklas Cassel <cassel@kernel.org>
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prev parent reply other threads:[~2025-04-10 6:11 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-09 9:51 [PATCH v2] PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up() Shawn Lin
2025-04-10 6:10 ` Niklas Cassel [this message]
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