From: Niklas Cassel <cassel@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: "Shawn Lin" <shawn.lin@rock-chips.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org
Subject: Re: [PATCH] PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up()
Date: Mon, 14 Apr 2025 12:06:09 +0200 [thread overview]
Message-ID: <Z_zeERoDtZ52kW0T@ryzen> (raw)
In-Reply-To: <gogw24yg4lfq77ime7qyurvkef5yvmkkwjxo6xch52fbszibax@diaxredvtcrh>
Hello Mani,
On Sun, Apr 13, 2025 at 07:54:28PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Apr 09, 2025 at 11:19:03AM +0200, Niklas Cassel wrote:
> >
> > It seems like we should really add a warning and a comment in
> > dw_pcie_link_up(), so that others don't get hit by this hard to debug issue!
> >
>
> Right. But I'm also wondering if we should use the 'Data Link Layer Link Active'
> bit in PCI Express Capability for checking link up. Qcom driver has been using
> it from the start and there are no reported issues. We could add this as the
> first fallback if the link_up callback is not provided.
Sounds like a good idea, but from looking at:
7.5.3.6 Link Capabilities Register (Offset 0Ch)
"
Data Link Layer Link Active Reporting Capable - For a Downstream Port,
this bit must be hardwired to 1b if the component supports the optional
capability of reporting the DL_Active state of the Data Link Control and
Management State Machine. For a hot-plug capable Downstream Port (as
indicated by the Hot-Plug Capable bit of the Slot Capabilities Register)
or a Downstream Port that supports Link speeds greater than 5.0 GT/s,
this bit must be hardwired to 1b.
For Upstream Ports and components that do not support this optional
capability, this bit must be hardwired to 0b.
"
It sounds like the the 'Data Link Layer Link Active' bit is optional,
or at least optional for Gen1 and Gen2.
Kind regards,
Niklas
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next prev parent reply other threads:[~2025-04-14 10:13 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-09 6:40 [PATCH] PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up() Shawn Lin
2025-04-09 8:30 ` Niklas Cassel
2025-04-09 9:09 ` Shawn Lin
2025-04-09 9:19 ` Niklas Cassel
2025-04-09 9:41 ` Shawn Lin
2025-04-13 14:24 ` Manivannan Sadhasivam
2025-04-14 10:06 ` Niklas Cassel [this message]
2025-04-14 11:15 ` Manivannan Sadhasivam
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