From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35DFDC54764 for ; Mon, 19 Feb 2024 09:57:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=s8TME54TaEb+GxIbhuICexur7DI0NiXPEo129Fs1rVA=; b=sV6nuAigmVQOPP ncIvI/3zpRGFFB3BcsFlx2oWxg4NlYyxfjNu3G2ZPgN8E2geO/GZciRo1DEvl5Ovp+m+3ogfjCYvy 0n8BTv1zbRQrM6NPJ+nXF5A9/v33FbeKRyE8Iu5zRCm8hf/avMd50iEEKn/ORudqrL+id1Me3C8nO LbmI0wyorPpatvLLdPkI2mTME5JMHquuvlHHQl6ZYhLnVGxK/58jJdy6kCSz39MhV2VZJnyoV9lHL yQdg99KnYBkffx03OHfkhTMKRTvoSaA1q+CyEEmr4Sk62L/SRBmseZZ8775dnncqstlJguk4ABGGu 0ePQdMNre3xoXw9fRBpg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rc0Og-00000009vq8-3FKR; Mon, 19 Feb 2024 09:57:14 +0000 Received: from perceval.ideasonboard.com ([213.167.242.64]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rc0Oe-00000009vnK-2QX3 for linux-rockchip@lists.infradead.org; Mon, 19 Feb 2024 09:57:14 +0000 Received: from pyrite.rasen.tech (h175-177-049-156.catv02.itscom.jp [175.177.49.156]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id C75A522A; Mon, 19 Feb 2024 10:56:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1708336622; bh=cGALYH9wpQXinBE3eJq7xfLma+au5VECNieEHnthuKI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fpeup+WDHVeleXZz+HQcp1EVHR0WdHnHJtHH7r5ksX+9I7w/nhM58/biMRMBzWI/w bzskCVZ7U9mWypYYHhexVCRyB5qOjH/dD1gXtfoAREOhOLncVjFTpH1GRn1+EWS/nr Y7vMcqd9ELEbkt29Esgnazgo1lnUBtqkHg3Ffj/U= Date: Mon, 19 Feb 2024 18:56:59 +0900 From: Paul Elder To: Laurent Pinchart Cc: linux-media@vger.kernel.org, Adam Ford , Alexander Stein , Dafna Hirschfeld , Heiko Stuebner , Helen Koike , Kieran Bingham , Tomi Valkeinen , linux-rockchip@lists.infradead.org Subject: Re: [PATCH v13 11/12] media: rkisp1: Fix endianness on raw streams on i.MX8MP Message-ID: References: <20240218204350.10916-1-laurent.pinchart@ideasonboard.com> <20240218204350.10916-12-laurent.pinchart@ideasonboard.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240218204350.10916-12-laurent.pinchart@ideasonboard.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240219_015712_865360_1F8A9C5D X-CRM114-Status: GOOD ( 28.32 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Hi Laurent, On Sun, Feb 18, 2024 at 10:43:49PM +0200, Laurent Pinchart wrote: > From: Paul Elder > > The i.MX8MP has extra register fields in the memory interface control > register for setting the output format, which work with the output > alignment format register for byte-swapping and LSB/MSB alignment. > > With processed and 8-bit raw streams, it doesn't cause any problems to > not set these, but with raw streams of higher bit depth the endianness > is swapped and the data is not aligned properly. > > Add support for setting these registers and plumb them in to fix this. > > Signed-off-by: Paul Elder > Signed-off-by: Laurent Pinchart > --- > Changes since v12: > > - Merge the output_format_mp and output_format_sp fields > - Set the MP output format in rkisp1_mp_config() > - Fix typo in commit message > > Changes since v6: > > - replace MP_OUTPUT_FORMAT feature flag with MAIN_STRIDE > > New in v6 > --- > .../platform/rockchip/rkisp1/rkisp1-capture.c | 52 +++++++++++++++++-- > .../platform/rockchip/rkisp1/rkisp1-regs.h | 8 +++ > 2 files changed, 56 insertions(+), 4 deletions(-) > > diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c > index 0efdf8513de0..accc16ad1432 100644 > --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c > +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c > @@ -48,14 +48,17 @@ enum rkisp1_plane { > * @fmt_type: helper filed for pixel format > * @uv_swap: if cb cr swapped, for yuv > * @yc_swap: if y and cb/cr swapped, for yuv > + * @byte_swap: if byte pairs are swapped, for raw > * @write_format: defines how YCbCr self picture data is written to memory > - * @output_format: defines sp output format > + * @output_format: defines the output format (RKISP1_CIF_MI_INIT_MP_OUTPUT_* for > + * the main path and RKISP1_MI_CTRL_SP_OUTPUT_* for the self path) > * @mbus: the mbus code on the src resizer pad that matches the pixel format > */ > struct rkisp1_capture_fmt_cfg { > u32 fourcc; > u32 uv_swap : 1; > u32 yc_swap : 1; > + u32 byte_swap : 1; > u32 write_format; > u32 output_format; > u32 mbus; > @@ -96,42 +99,50 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = { > .fourcc = V4L2_PIX_FMT_YUYV, > .uv_swap = 0, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, > .mbus = MEDIA_BUS_FMT_YUYV8_2X8, > }, { > .fourcc = V4L2_PIX_FMT_UYVY, > .uv_swap = 0, > .yc_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, > .mbus = MEDIA_BUS_FMT_YUYV8_2X8, > }, { > .fourcc = V4L2_PIX_FMT_YUV422P, > .uv_swap = 0, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, > .mbus = MEDIA_BUS_FMT_YUYV8_2X8, > }, { > .fourcc = V4L2_PIX_FMT_NV16, > .uv_swap = 0, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, > .mbus = MEDIA_BUS_FMT_YUYV8_2X8, > }, { > .fourcc = V4L2_PIX_FMT_NV61, > .uv_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, > .mbus = MEDIA_BUS_FMT_YUYV8_2X8, > }, { > .fourcc = V4L2_PIX_FMT_NV16M, > .uv_swap = 0, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, > .mbus = MEDIA_BUS_FMT_YUYV8_2X8, > }, { > .fourcc = V4L2_PIX_FMT_NV61M, > .uv_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, > .mbus = MEDIA_BUS_FMT_YUYV8_2X8, > }, { > .fourcc = V4L2_PIX_FMT_YVU422M, > .uv_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, > .mbus = MEDIA_BUS_FMT_YUYV8_2X8, > }, > /* yuv400 */ > @@ -139,6 +150,7 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = { > .fourcc = V4L2_PIX_FMT_GREY, > .uv_swap = 0, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400, > .mbus = MEDIA_BUS_FMT_YUYV8_2X8, > }, > /* yuv420 */ > @@ -146,81 +158,107 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = { > .fourcc = V4L2_PIX_FMT_NV21, > .uv_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420, > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, > }, { > .fourcc = V4L2_PIX_FMT_NV12, > .uv_swap = 0, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420, > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, > }, { > .fourcc = V4L2_PIX_FMT_NV21M, > .uv_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420, > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, > }, { > .fourcc = V4L2_PIX_FMT_NV12M, > .uv_swap = 0, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420, > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, > }, { > .fourcc = V4L2_PIX_FMT_YUV420, > .uv_swap = 0, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420, > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, > }, { > .fourcc = V4L2_PIX_FMT_YVU420, > .uv_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420, > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, > }, > /* raw */ > { > .fourcc = V4L2_PIX_FMT_SRGGB8, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8, > .mbus = MEDIA_BUS_FMT_SRGGB8_1X8, > }, { > .fourcc = V4L2_PIX_FMT_SGRBG8, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8, > .mbus = MEDIA_BUS_FMT_SGRBG8_1X8, > }, { > .fourcc = V4L2_PIX_FMT_SGBRG8, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8, > .mbus = MEDIA_BUS_FMT_SGBRG8_1X8, > }, { > .fourcc = V4L2_PIX_FMT_SBGGR8, > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8, > .mbus = MEDIA_BUS_FMT_SBGGR8_1X8, > }, { > .fourcc = V4L2_PIX_FMT_SRGGB10, > + .byte_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10, > .mbus = MEDIA_BUS_FMT_SRGGB10_1X10, > }, { > .fourcc = V4L2_PIX_FMT_SGRBG10, > + .byte_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10, > .mbus = MEDIA_BUS_FMT_SGRBG10_1X10, > }, { > .fourcc = V4L2_PIX_FMT_SGBRG10, > + .byte_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10, > .mbus = MEDIA_BUS_FMT_SGBRG10_1X10, > }, { > .fourcc = V4L2_PIX_FMT_SBGGR10, > + .byte_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10, > .mbus = MEDIA_BUS_FMT_SBGGR10_1X10, > }, { > .fourcc = V4L2_PIX_FMT_SRGGB12, > + .byte_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12, > .mbus = MEDIA_BUS_FMT_SRGGB12_1X12, > }, { > .fourcc = V4L2_PIX_FMT_SGRBG12, > + .byte_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12, > .mbus = MEDIA_BUS_FMT_SGRBG12_1X12, > }, { > .fourcc = V4L2_PIX_FMT_SGBRG12, > + .byte_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12, > .mbus = MEDIA_BUS_FMT_SGBRG12_1X12, > }, { > .fourcc = V4L2_PIX_FMT_SBGGR12, > + .byte_swap = 1, > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12, > .mbus = MEDIA_BUS_FMT_SBGGR12_1X12, > }, > }; > @@ -484,10 +522,12 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap) > */ > if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) { > reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT); > - if (cap->pix.cfg->yc_swap) > + if (cap->pix.cfg->yc_swap || cap->pix.cfg->byte_swap) > reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES; > else > reg &= ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES; > + > + reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_LSB_ALIGNMENT; > rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT, reg); > } > > @@ -557,6 +597,8 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap) > cap->pix.cfg->output_format | > RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE; > rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); > + > + rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, cap->pix.cfg->output_format); I think you're missing the analogous register setting for the main path. Paul > } > > static void rkisp1_mp_disable(struct rkisp1_capture *cap) > @@ -943,6 +985,7 @@ static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap) > struct rkisp1_device *rkisp1 = cap->rkisp1; > struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1]; > bool has_self_path = rkisp1_has_feature(rkisp1, SELF_PATH); > + u32 reg; > > cap->ops->set_data_path(cap); > cap->ops->config(cap); > @@ -962,8 +1005,9 @@ static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap) > */ > if (!has_self_path || !other->is_streaming) { > /* force cfg update */ > - rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, > - RKISP1_CIF_MI_INIT_SOFT_UPD); > + reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_INIT); > + reg |= RKISP1_CIF_MI_INIT_SOFT_UPD; > + rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, reg); > rkisp1_set_next_buf(cap); > } > spin_unlock_irq(&cap->buf.lock); > diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h > index 3b19c8411360..762243016f05 100644 > --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h > +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h > @@ -144,6 +144,14 @@ > /* MI_INIT */ > #define RKISP1_CIF_MI_INIT_SKIP BIT(2) > #define RKISP1_CIF_MI_INIT_SOFT_UPD BIT(4) > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400 (0 << 5) > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420 (1 << 5) > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422 (2 << 5) > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV444 (3 << 5) > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12 (4 << 5) > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8 (5 << 5) > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_JPEG (6 << 5) > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10 (7 << 5) > > /* MI_CTRL_SHD */ > #define RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED BIT(0) _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip