From: "Fabio Estevam" <festevam@nabladev.com>
To: "Shawn Lin" <shawn.lin@rock-chips.com>
Cc: "Stephen Boyd" <sboyd@kernel.org>,
heiko@sntech.de, "Brian Masney" <bmasney+clk@redhat.com>,
"Jerome Brunet" <jbrunet+clk@baylibre.com>,
linux-rockchip@lists.infradead.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 2/2] clk: rockchip: fix wrong PMU CLKSEL register on rv1103b
Date: Sat, 10 Oct 2026 21:26:58 +0200 [thread overview]
Message-ID: <a44bfaca-9c4e-dc0c-6f83-364a7953bb44@nabladev.com> (raw)
In-Reply-To: <1791641839-74584-3-git-send-email-shawn.lin@rock-chips.com>
Hi Shawn,
On Saturday, October 10, 2026 11:17 -03, Shawn Lin <shawn.lin@rock-chips.com> wrote:
> clk_32k and dbclk_pmu_gpio0 use RK3568_PMU_CLKSEL_CON(0), which is the
> wrong SoC macro and resolves to 0x100 in the PERICRU region instead of
> the RV1103B PMUCRU register at 0x70300. Reading or setting these clocks
> would access an unrelated register.
>
> Use RV1103B_PMUCLKSEL_CON(0), as already done for the XIN_RC_SRC clock
> in the same file.
>
> Fixes: 3e65e426d457 ("clk: rockchip: Add clock controller for the RV1103B")
> Cc: Fabio Estevam <festevam@nabladev.com>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Thanks for the fix.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
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prev parent reply other threads:[~2026-10-10 19:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-10 14:17 [PATCH 0/2] Two fixes for clk driver of RV1103B and RK3562 Shawn Lin
2026-10-10 14:17 ` [PATCH 1/2] clk: rockchip: fix wrong gate register for clk_gpll_mux_to_ddr on rk3562 Shawn Lin
2026-10-10 14:17 ` [PATCH 2/2] clk: rockchip: fix wrong PMU CLKSEL register on rv1103b Shawn Lin
2026-10-10 19:26 ` Fabio Estevam [this message]
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