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Received: by smtp.zohomail.com with SMTPS id 1794322316098419.50846392536164; Tue, 10 Nov 2026 06:51:56 -0800 (PST) Received: by venus (Postfix, from userid 1000) id F1A01180354; Tue, 10 Nov 2026 15:51:46 +0100 (CET) Date: Tue, 10 Nov 2026 15:51:46 +0100 From: Sebastian Reichel To: aiyengar1990@gmail.com Cc: Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH 1/5] dt-bindings: iommu: arm,smmu-v3: allow a power domain Message-ID: References: <20261110-smmu-v3-pcie-pd-v1-0-628819ca44b9@gmail.com> <20261110-smmu-v3-pcie-pd-v1-1-628819ca44b9@gmail.com> X-Archived-By: MIME-Version: 1.0 In-Reply-To: <20261110-smmu-v3-pcie-pd-v1-1-628819ca44b9@gmail.com> X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.13.1.5.4/294.310.16 X-ZohoMailClient: External X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261110_065208_363725_4DA2BB39 X-CRM114-Status: GOOD ( 18.83 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============5411456435872998793==" Sender: "Linux-rockchip" X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 --===============5411456435872998793== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="tfqghsv2wlsgx7bh" Content-Disposition: inline --tfqghsv2wlsgx7bh Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH 1/5] dt-bindings: iommu: arm,smmu-v3: allow a power domain MIME-Version: 1.0 Hi, On Tue, Nov 10, 2026 at 07:11:48AM +0000, Arun Iyengar via B4 Relay wrote: > From: Arun Iyengar >=20 > An SMMUv3 instance can sit in a switchable power domain of the SoC, for > example the MMU-600 in front of the PCIe controllers on the Rockchip > RK3588, which is part of the PCIe power domain. If the domain is not > described, nothing keeps it powered while the SMMU is bound, and any > register access after it has been turned off as unused stalls the > interconnect. >=20 > Allow a single power-domains entry, as arm,smmu.yaml already does for > the earlier SMMU architectures. >=20 > Signed-off-by: Arun Iyengar > --- Reviewed-by: Sebastian Reichel Greetings, -- Sebastian > Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 3 +++ > 1 file changed, 3 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/D= ocumentation/devicetree/bindings/iommu/arm,smmu-v3.yaml > index 3c044e4f03d4..c8f22dfdb1db 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml > @@ -63,6 +63,9 @@ properties: > =20 > msi-parent: true > =20 > + power-domains: > + maxItems: 1 > + > nvidia,cmdqv: > description: | > A phandle to its pairing CMDQV extension for an implementation on = NVIDIA >=20 > --=20 > 2.55.0 >=20 >=20 >=20 --tfqghsv2wlsgx7bh Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAmrzL34ACgkQ2O7X88g7 +pqJrw/+Ltixuq2mwS/7jblulvQQALfQna4bWRC1zreexGhF+leoXqP9JEMhCnkp Vr3wOBovLKA//DQokcLKXgDGqVS21CBMdTAEp2Gc+G0N0VHZzdSP7i3QCkr9qNZI vPm9hifWU277QF5SgT/YCR94Jt8m46KSkFNiaeq2dTUBi+/TpYO1y1UxvNnlBm8H ySl3PLGGBj909ezmEy12KLVHxYAPM3SKAbE6dr7Uyo3B2yuMp5uY1TPdYbJpNi4+ s/qBdbgxBqPVWVhRspqwjcJKpc2jnv1aLQjZsHCulAxY6iOnGscDwHgCnerj7xw2 XJOJ+cmGi2CvqRYloutaEx3DFDW0ANLaOvxLBe43c8jwuDP72eeM+Bl4JnNxQOZX uVu6498a/JQxBCXyo0IW/vEUQ/VhCo6bG7CaLHIWmuX/gVH0DNCuz43JFInaZaCz lHffjGUeQNGigfx+zlTTu1Ng0rqBA6qKnva8gOUE2AvFkWD3lYh7MWuZWy4Foz6i g2FEtxt2CfNYpzm6/XE5Sp5ayNqO0l3N2Y+m2W413Ae8Pe5dmtZmNekDmJOLKzYq PWNKmQ16cANFsiA0Zq8fL7p4EArT1cC7o37lWeKdJJdodL+edfTFWmee0YmmrTOA lsBVO1mkefW/Kf+L2CL8+DoN0EUu7+qa7rVBLxOlkPB+b3A8UsU= =xEf6 -----END PGP SIGNATURE----- --tfqghsv2wlsgx7bh-- --===============5411456435872998793== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip --===============5411456435872998793==--