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Received: by smtp.zohomail.com with SMTPS id 1794322827521487.8316939248318; Tue, 10 Nov 2026 07:00:27 -0800 (PST) Received: by venus (Postfix, from userid 1000) id D82A2180354; Tue, 10 Nov 2026 16:00:17 +0100 (CET) Date: Tue, 10 Nov 2026 16:00:17 +0100 From: Sebastian Reichel To: aiyengar1990@gmail.com Cc: Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH 4/5] arm64: dts: rockchip: add the PCIe power domain to the RK3588 PCIe SMMU Message-ID: References: <20261110-smmu-v3-pcie-pd-v1-0-628819ca44b9@gmail.com> <20261110-smmu-v3-pcie-pd-v1-4-628819ca44b9@gmail.com> X-Archived-By: MIME-Version: 1.0 In-Reply-To: <20261110-smmu-v3-pcie-pd-v1-4-628819ca44b9@gmail.com> X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.13.1.5.4/294.310.16 X-ZohoMailClient: External X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261110_070037_784422_045D5080 X-CRM114-Status: GOOD ( 22.63 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============7205868830868012256==" Sender: "Linux-rockchip" X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 --===============7205868830868012256== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="yvnwakyswhfsguxx" Content-Disposition: inline --yvnwakyswhfsguxx Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH 4/5] arm64: dts: rockchip: add the PCIe power domain to the RK3588 PCIe SMMU MIME-Version: 1.0 Hi, On Tue, Nov 10, 2026 at 07:11:51AM +0000, Arun Iyengar via B4 Relay wrote: > From: Arun Iyengar >=20 > The MMU-600 for the PCIe controllers (mmu600_pcie) is enabled for every > RK3588 board, but its node does not describe that it lives in > RK3588_PD_PCIE. It only works today because TF-A leaves the domain on at > boot and, on most boards, an enabled PCIe controller holds it on later. >=20 > On a board that disables all PCIe controllers using that domain (the > Orange Pi 5 with its M.2 slot in SATA mode is one), genpd powers > PD_PCIE off as unused after boot while arm-smmu-v3 is still bound. Then > at reboot arm_smmu_device_shutdown() writes CR0 and polls CR0ACK on the > unpowered block, which stalls the bus: the kernel never reaches > "reboot: Restarting system" and the board only comes back once the > watchdog fires. >=20 > Describe the power domain, so genpd keeps it on for as long as the SMMU > is bound. >=20 > Fixes: da92d3dfc871 ("arm64: dts: rockchip: enable the mmu600_pcie IOMMU = on the rk3588 SoC") > Signed-off-by: Arun Iyengar > --- > arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 + > 1 file changed, 1 insertion(+) >=20 > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/b= oot/dts/rockchip/rk3588-base.dtsi > index aa69fd3793fd..bcd342c025c9 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi > @@ -560,6 +560,7 @@ mmu600_pcie: iommu@fc900000 { > ; > interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; > #iommu-cells =3D <1>; > + power-domains =3D <&power RK3588_PD_PCIE>; The TRM says the power domain of MMU600_PCIE is PD_PHP, not PD_PCIE. See Table 7-1 RK3588 Voltage Domain and Power Domain Summary around page 1096 (depending on specific TRM version). Note, that PD_PCIE is a child of PD_PHP, so it makes sense that PD_PCIE also works. Greetings, -- Sebastian > }; > =20 > mmu600_php: iommu@fcb00000 { >=20 > --=20 > 2.55.0 >=20 >=20 >=20 --yvnwakyswhfsguxx Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAmrzMYEACgkQ2O7X88g7 +prfPw/9H7V6CFJtfI0s9f5zQ1tXpHmng97aGYhRQAxloE/LcvZHpFI8zHFOAL+3 /BQfGKhYVHxw0VEO4VSVrIbaLWag1mtFtYfjINdR5/uT6937ctWfyskTfMuKf/35 O3nOwz8Uihhq3ZbA+AFJ+DLbUiRs7+Ka7rn4IxvDE/YEZrVPFJIRmU/iJ5NZTiDs u8AVATgGiVEmYXFkrqUr3siaEB5QiITUOkv8F4y5i9xYcrqnRr+9LrwjXVsjVpn+ cySgWnAySJ13eX55L4XktWLXiqd26EaK7dRTcWsNm6mACod8BP1sGtDJkS310fFv Utzx30B9Qh7ThWXF2HwdmeqSGfzWFc54k8IHtmx7PcpKkxmOFXG5+e7gOw1IMCE0 Ro9SQxIwJ44twPtPyuQyA/nzqvui8ZmzFhZ9TmuKjyuR1tOLmg1546WVLJroN3+B ceLNYAhT94Xopbf4C1WAA8WWOSEuhU7ILyyDB+LqVQEG8YtaP6d9wFq0vRDxKbXj WITuytLrKkMWWjwXtq2qWko1HLDCHv1SV/1lmw7Vxye2Gx8mLIjnrRXgRVfhcmZA TC7g/FJ3/oEvKSbf9OrE5LglaqBWGgwbzN+e/g7UCoQnfHKOwHB9phFeOj7nUTvW /zzCKbC+DQ+HjRbMKlP9bEw/GgJebMSK+fDAM7d68zim0FCJ5Jo= =Q6ux -----END PGP SIGNATURE----- --yvnwakyswhfsguxx-- --===============7205868830868012256== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip --===============7205868830868012256==--