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Received: by smtp.zohomail.com with SMTPS id 1794501486774956.4551935908814; Thu, 12 Nov 2026 08:38:06 -0800 (PST) Received: by venus (Postfix, from userid 1000) id CBC96180570; Thu, 12 Nov 2026 17:38:01 +0100 (CET) Date: Thu, 12 Nov 2026 17:38:01 +0100 From: Sebastian Reichel To: aiyengar1990@gmail.com Cc: Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Pranjal Shrivastava , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Shawn Lin , Simon Xue , Finley Xiao Subject: Re: [PATCH v2 1/4] dt-bindings: iommu: arm,smmu-v3: Allow a clock and a reset Message-ID: References: <20261112-smmu-v3-pcie-pd-v2-0-3a77bbb6b2c4@gmail.com> <20261112-smmu-v3-pcie-pd-v2-1-3a77bbb6b2c4@gmail.com> X-Archived-By: MIME-Version: 1.0 In-Reply-To: <20261112-smmu-v3-pcie-pd-v2-1-3a77bbb6b2c4@gmail.com> X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.13.1.5.4/294.497.36 X-ZohoMailClient: External X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261112_163819_439535_9ADC2E44 X-CRM114-Status: GOOD ( 23.54 ) X-Spam-Score: -0.2 (/) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============7996425645949215044==" Sender: "Linux-rockchip" X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 --===============7996425645949215044== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="axwnauw6ygxsatcc" Content-Disposition: inline --axwnauw6ygxsatcc Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v2 1/4] dt-bindings: iommu: arm,smmu-v3: Allow a clock and a reset MIME-Version: 1.0 Hi, On Thu, Nov 12, 2026 at 08:20:22AM +0000, Arun Iyengar via B4 Relay wrote: > From: Arun Iyengar >=20 > Some SoCs feed the SMMUv3 from a clock that the OS controls. On the > Rockchip RK3588 the MMU-600 for PCIe runs from ACLK_MMU_PCIE, whose only > other consumers are the PCIe controllers. When no PCIe controller is > enabled, the clock framework gates it as unused, and the SMMU can no > longer be accessed. The same SMMU also has a reset line in the CRU, > SRST_A_MMU_PCIE. >=20 > Allow a single clock and a single reset, so that both can be described. > The architecture defines no clock or reset inputs; the MMU-600 TRM lists > one clock and one reset signal, and the one integration that needs this > has one of each. An implementation with more clocks or resets can add > them with names and a specific compatible. You can trim that down quite a bit. Don't take over AI text 1:1. >=20 > Link: https://support.arm.com/documentation/100310/0202/Signal-descriptio= ns/Clock-and-reset-signals > Signed-off-by: Arun Iyengar > --- > Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 11 +++++++++++ > 1 file changed, 11 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/D= ocumentation/devicetree/bindings/iommu/arm,smmu-v3.yaml > index 3c044e4f03d4..29b81b4fb650 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml > @@ -63,6 +63,17 @@ properties: > =20 > msi-parent: true > =20 > + clocks: > + maxItems: 1 > + description: > + Clock of the SMMU's register and memory interfaces, on SoCs where = the > + OS has to keep it running. > + > + resets: > + maxItems: 1 > + description: > + Reset of the SMMU, on SoCs where it is controlled by the OS. The ', on SoCs where it is controlled by the OS.' is completley useless for both. You need to review your AI output and not take it over without doing any thinking yourself. Greetings, -- Sebastian > nvidia,cmdqv: > description: | > A phandle to its pairing CMDQV extension for an implementation on = NVIDIA >=20 --axwnauw6ygxsatcc Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAmr162kACgkQ2O7X88g7 +pp8TA/6AvacCvvFrtEJ9uEds7WG2pqKKql3tDgbixgwWbdt4jb9Uno84nloIhoH j3vlNNjCs1I7sfA9KxDhGSbqZM1Q3EPis3hoktky7vefI8Gk/g6hzxilqwOmKrKK GJRIRdKDCb5osCgwrqpENYPD8XweBOFu6DKigsdQG/Y+14WfJM2q9DF5mqhwleZL KTU2j7l0uIeDzrXVhCCQR10zMOJBo1iRL6JZmkvGEv2ph4CsdB3NjV0eG01CVK86 TRnfdKSvT3+L6IPOu7XlCoHQ4BP7wtWOB4Dpb13SxjNXGBSWu0QV6XbZp5lulmdU d2mNUCrU7P42tdgIVSwGVBwYYyymCvqEnukqAEucWjrvGFD8eSZM2wSANBlbnijS A5qcPBVfoTjTIUVZg2/bK7yf6mU1oY6kLSZ3w5vIlJ2pNFemTYAv1ZWfs2QPOGqw 6Cro+Q2DTCuU8eSqOVEmzP4BibPeDdNz3M91VvdzW5AD1WXHz4ZWrpueYE4ZtvZi BOKFfh5QakYt1YXvQU1iw1Nzg8CMyoaLPiZS4vaZg9eK5Z972fm1QAwoMs9jsbNH hkL/pRIO+517K3U8QHdFJtJevY0ta1vna0itB7GH8IsR0ntE6E6vpRaUA74VsRr4 hD977z7kgv3TjVM1pGp0P4VybhXtvwcU7M4hJXMTRuEsOzwbx6A= =Wdr0 -----END PGP SIGNATURE----- --axwnauw6ygxsatcc-- --===============7996425645949215044== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip --===============7996425645949215044==--