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auth=pass smtp.auth=dsimic@manjaro.org smtp.mailfrom=dsimic@manjaro.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_074003_347753_18F4E8A2 X-CRM114-Status: GOOD ( 24.69 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Hello Detlev, On 2024-08-23 15:34, Detlev Casanova wrote: > On Friday, 23 August 2024 01:41:44 EDT Dragan Simic wrote: >> Hello Detlev, >> >> Please see a comment below. >> >> On 2024-08-22 23:15, Detlev Casanova wrote: >> > From: Shawn Lin >> > >> > Some Rockchip devices put the phase settings into the dw_mmc >> > controller. >> > >> > When the feature is present, the ciu-drive and ciu-sample clocks are >> > not used and the phase configuration is done directly through the mmc >> > controller. >> > >> > Signed-off-by: Shawn Lin >> > Signed-off-by: Detlev Casanova >> > Acked-by: Shawn Lin >> > --- >> > >> > drivers/mmc/host/dw_mmc-rockchip.c | 171 +++++++++++++++++++++++++++-- >> > 1 file changed, 160 insertions(+), 11 deletions(-) >> > >> > diff --git a/drivers/mmc/host/dw_mmc-rockchip.c >> > b/drivers/mmc/host/dw_mmc-rockchip.c >> > index b07190ba4b7a..2748f9bf2691 100644 >> > --- a/drivers/mmc/host/dw_mmc-rockchip.c >> > +++ b/drivers/mmc/host/dw_mmc-rockchip.c >> > @@ -15,7 +15,17 @@ >> > >> > #include "dw_mmc.h" >> > #include "dw_mmc-pltfm.h" >> > >> > -#define RK3288_CLKGEN_DIV 2 >> > +#define RK3288_CLKGEN_DIV 2 >> > +#define SDMMC_TIMING_CON0 0x130 >> > +#define SDMMC_TIMING_CON1 0x134 >> > +#define ROCKCHIP_MMC_DELAY_SEL BIT(10) >> > +#define ROCKCHIP_MMC_DEGREE_MASK 0x3 >> > +#define ROCKCHIP_MMC_DEGREE_OFFSET 1 >> > +#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 >> > +#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << >> > ROCKCHIP_MMC_DELAYNUM_OFFSET) >> > +#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 >> > +#define HIWORD_UPDATE(val, mask, shift) \ >> > + ((val) << (shift) | (mask) << ((shift) + 16)) >> > >> > static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 >> > >> > }; >> > >> > @@ -24,8 +34,143 @@ struct dw_mci_rockchip_priv_data { >> > >> > struct clk *sample_clk; >> > int default_sample_phase; >> > int num_phases; >> > >> > + int internal_phase; >> > >> > }; >> >> It might be good to declare internal_phase as "unsigned int >> internal_phase:1", >> i.e. as a bit field, which isn't going to save some memory in this >> particular >> case, but it would show additional attention to detail. > > In that case, I would go with a bool instead of int, that makes things > even clearer. My suggestion to use "unsigned int internal_phase:1" actually takes inspiration from the ASoC code, in which such bit fields are used quite a lot, even when using them actually doesn't save space. In this particular case, using plain bool would make sense, but I still think that using an "unsigned int internal_phase:1" bit field would fit better, because it would show the intention to possibly save a bit of RAM at some point. OTOH, I don't think that using bool with such bit fields would actually work cleanly, because bool actually resolves to int that's a signed type. _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip