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Wed, 5 Apr 2023 07:50:38 -0400 (EDT) Message-ID: Date: Wed, 5 Apr 2023 20:50:37 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v3 10/11] PCI: rockchip: Don't advertise MSI-X in PCIe capabilities Content-Language: en-US To: Rick Wertenbroek , alberto.dassatti@heig-vd.ch Cc: damien.lemoal@opensource.wdc.com, xxm@rock-chips.com, Shawn Lin , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Heiko Stuebner , Johan Jonker , Brian Norris , Caleb Connolly , Corentin Labbe , Arnaud Ferraris , Lin Huang , Judy Hsiao , Hugh Cole-Baker , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20230404082426.3880812-1-rick.wertenbroek@gmail.com> <20230404082426.3880812-11-rick.wertenbroek@gmail.com> From: Damien Le Moal In-Reply-To: <20230404082426.3880812-11-rick.wertenbroek@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230405_045045_457948_063F495F X-CRM114-Status: GOOD ( 24.09 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org On 4/4/23 17:24, Rick Wertenbroek wrote: > The RK3399 PCIe endpoint controller cannot generate MSI-X IRQs. > This is documented in the RK3399 technical reference manual (TRM) > section 17.5.9 "Interrupt Support". > > MSI-X capability should therefore not be advertised. Remove the > MSI-X capability by editing the capability linked-list. The > previous entry is the MSI capability, therefore get the next > entry from the MSI-X capability entry and set it as next entry > for the MSI capability. This in effect removes MSI-X from the list. > > Linked list before : MSI cap -> MSI-X cap -> PCIe Device cap -> ... > Linked list now : MSI cap -> PCIe Device cap -> ... > > Signed-off-by: Rick Wertenbroek > --- > drivers/pci/controller/pcie-rockchip-ep.c | 15 +++++++++++++++ > drivers/pci/controller/pcie-rockchip.h | 5 +++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c > index 924b95bd736c..20c768287870 100644 > --- a/drivers/pci/controller/pcie-rockchip-ep.c > +++ b/drivers/pci/controller/pcie-rockchip-ep.c > @@ -510,6 +510,7 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) > size_t max_regions; > struct pci_epc_mem_window *windows = NULL; > int err, i; > + u32 cfg_msi, cfg_msix_cp; > > ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); > if (!ep) > @@ -584,6 +585,20 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) > > ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; > Nit: Adding a comment here about what this is doing and why would be nice. E.g. something like: /* * MSI-X is not supported but the controller still advertises by default * the MSI-X capability, which can lead to the RC-side attempting to use * MSI-X. Avoid this by skipping the MSI-X capability entry in the * chain of PCIe capabilities: get the next pointer from the * MSI-X entry and set that in the MSI capability entry. This way * the MSI-X entry is skipped (left out of the linked-list). */ > + cfg_msi = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > + > + cfg_msi &= ~ROCKCHIP_PCIE_EP_MSI_CP1_MASK; > + > + cfg_msix_cp = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + > + ROCKCHIP_PCIE_EP_MSIX_CAP_REG) & > + ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK; > + > + cfg_msi |= cfg_msix_cp; > + > + rockchip_pcie_write(rockchip, cfg_msi, > + PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > + > rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, PCIE_CLIENT_CONFIG); > > return 0; > diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h > index 1558eae298ae..a21070ea7166 100644 > --- a/drivers/pci/controller/pcie-rockchip.h > +++ b/drivers/pci/controller/pcie-rockchip.h > @@ -226,6 +226,8 @@ > #define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4 > #define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19) > #define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90 > +#define ROCKCHIP_PCIE_EP_MSI_CP1_OFFSET 8 > +#define ROCKCHIP_PCIE_EP_MSI_CP1_MASK GENMASK(15, 8) > #define ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET 16 > #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17 > #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17) > @@ -233,6 +235,9 @@ > #define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK GENMASK(22, 20) > #define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(16) > #define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24) > +#define ROCKCHIP_PCIE_EP_MSIX_CAP_REG 0xb0 > +#define ROCKCHIP_PCIE_EP_MSIX_CAP_CP_OFFSET 8 > +#define ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK GENMASK(15, 8) > #define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1 > #define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3 > #define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) \ _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip