From: Daniel Schultz <d.schultz@phytec.de>
To: Heiko Stuebner <heiko@sntech.de>
Cc: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, w.egorov@phytec.de
Subject: Re: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing
Date: Mon, 5 Mar 2018 16:57:13 +0100 [thread overview]
Message-ID: <cecf3c08-d43d-c340-c5ff-30e41e338469@phytec.de> (raw)
In-Reply-To: <3530074.WSbKf9j6h0@phil>
Hi,
On 03/05/2018 03:15 PM, Heiko Stuebner wrote:
> Hi Daniel,
>
> Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz:
>> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
>> Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
>>
>> Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
>> ---
>>
>> The binding will be added with the next merge of net-next:
>> https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit/?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570
https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/log/Documentation/devicetree/bindings/net/ti,dp83867.txt
If I search in the master branch, I get the patch. Did I searched wrong?
Daniel
> I did find the commit, but no related change of the dp83867 dt binding
> document [0], including a review by dt-maintainers.
>
> While your property does not look overly complicated, the binding
> should be updated nontheless.
>
>
> Heiko
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/log/Documentation/devicetree/bindings/net/ti,dp83867.txt?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570
>
>> arch/arm/boot/dts/rk3288-phycore-som.dtsi | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
>> index bdd80aa..e60535d 100644
>> --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
>> +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
>> @@ -141,6 +141,7 @@
>> ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> enet-phy-lane-no-swap;
>> + ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
>> };
>> };
>> };
>>
>
--
Mit freundlichen Grüßen,
With best regards,
Daniel Schultz
- Entwicklung -
Tel.: +49 6131 92 21 457
d.schultz@phytec.de
www.phytec.de
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next prev parent reply other threads:[~2018-03-05 15:57 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-05 12:45 [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing Daniel Schultz
2018-03-05 14:15 ` Heiko Stuebner
2018-03-05 15:57 ` Daniel Schultz [this message]
2018-03-05 17:04 ` Heiko Stübner
2018-03-05 20:25 ` Heiko Stübner
2018-03-05 21:08 ` Heiko Stübner
2018-03-06 9:59 ` Daniel Schultz
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